On-chip cache device and read-write method

Abstract

The invention provides an on-chip cache device and a read-write method, and the device comprises a read-write processing module, a high-speed cache module and a memory module, wherein the read-write processing module is respectively connected with the cache module and the memory module, and the read-write processing module is used for storing messages in the cache module and the memory module, reading the messages stored in the cache module and the memory module, and transferring the messages cached in the cache module to the memory module; the high-speed cache module is connected with the memory module through the read-write processing module, and the high-speed cache module comprises at least one cache register and is used for temporarily caching messages; and the memory module is connected with the read-write processing module and is used for transferring the message cached by the high-speed cache module. The multiple messages are cached to be written into the buffer at the same time, the chip storage space utilization rate is increased, the storage area is reduced, and chip power consumption is reduced.

Description

technical field [0001] The present application relates to the field of communication chips, in particular to an on-chip cache device and method. Background technique [0002] In the network switching engine, due to the requirements of performance index improvement and the limitation of chip area, resources and industry, it is impossible for the chip to meet the demand of performance improvement by increasing the main frequency and stacking resources without limit, so an implementation is urgently needed. The low redundancy of chip space and low area consumption realize the improvement of chip performance. [0003] In the existing chip design, the resource space of the chip is used in different ways in different application scenarios. In the big data processing scenario, due to the generation of small packets, the storage in the chip can only be stored by row address, and the chip processes small packets. At this time, each row address can only store a small packet message, ...

AI Technical Summary

Problems solved by technology

[0003] In the existing chip design, the resource space of the chip is used in different ways in different application scenarios. In the big data processing scenario, due to the generation of small packets, the storage in the chip can only be stored by row address, and the chip processes small packets. At this time, each row address can only store a small packet message, which wastes a lot of storage space. In order to process the small packet message, the chip design has a large storage area, resulting in the problem of high power consumption.

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