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Semiconductor memory device

A technology for memory devices and semiconductors, applied in semiconductor devices, electric solid state devices, electrical components, etc., and can solve problems such as limitations

Pending Publication Date: 2021-10-29
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the degree of integration of two-dimensional semiconductor elements is increasing due to the need for very expensive equipment such as miniaturized photolithography tools for patterning, but is still limited

Method used

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  • Semiconductor memory device
  • Semiconductor memory device
  • Semiconductor memory device

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0039] Figure 1A and Figure 1B is a circuit diagram of a unit cell of a semiconductor memory device according to some example embodiments. figure 2 is for illustration Figure 1A A diagram of the operation of the unit cell.

[0040] refer to Figure 1A and figure 2, The semiconductor memory device according to some example embodiments may include a semiconductor region including a p-type impurity region (p+), an n-type impurity region (n+), and ) between the base region (base).

[0041] The semiconductor memory device may include, for example, a first gate electrode GE1 and a second gate electrode GE2 disposed on a base region (base). The first gate electrode GE1 may be closer to the p-type impurity region (p+) than the second gate electrode GE2 to the p-type impurity region (p+). The first control transistor T1 may be defined by a first gate electrode GE1 and a base region (base). The second control transistor T2 may be defined by a second gate electrode GE2 and a ba...

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PUM

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Abstract

Provided is a semiconductor memory device. The semiconductor memory device comprises a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region between the first impurity region and the second impurity region, a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film, wherein the first gate electrode penetrates the channel region and the first gate insulating film is between the first gate electrode and the semiconductor pattern.

Description

technical field [0001] Example embodiments relate to semiconductor memory devices and / or methods for manufacturing the same, and more particularly, to three-dimensional semiconductor memory devices having improved electrical characteristics and / or methods for manufacturing the same. Background technique [0002] In order to meet the expected performance and low price demanded by consumers, it is required / pursued to increase the degree of integration of semiconductor elements. In the case of semiconductor elements, since the degree of integration is an important factor in determining the price of a product, a particularly increased degree of integration is required / pursued. [0003] In the case of a conventional two-dimensional or planar semiconductor element, since its degree of integration is mainly determined by the area occupied by a unit memory cell, the degree of integration is greatly affected by the level of fine pattern formation technology. However, the degree of i...

Claims

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Application Information

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IPC IPC(8): H01L27/11563H01L27/11578H01L27/11568
CPCH10B43/00H10B43/30H10B43/20H01L27/1027H01L29/7455H01L29/0676H10B12/00H01L29/74H01L29/42308H10B41/70H10B41/20H10B41/35H10B41/41H10B41/50
Inventor 李炅奂金容锡金炫哲山田悟柳成原弘载昊
Owner SAMSUNG ELECTRONICS CO LTD