Satellite modem synchronous interface data processing system and method

Abstract

The invention relates to a satellite modem synchronous interface data processing system and method. The system comprises a direct digital synthesizer module (DDS module), a clock control module and a first-in first-out data cache module (FIFO cache module). According to the invention, the clock control module is used for controlling the working clock frequency of a V.35 synchronous interface, so that the data in the FIFO cache module is stable, does not overflow and is not read null in a certain interval, thereby ensuring the stable transmission of the data of the synchronous interface. In the DTE working mode, the clock control module and the DDS module do not work, the service rate of the modem is improved, so as to be larger than a V.35 synchronous interface working clock generated by DTE equipment, the difference between the service rate and the clock frequency is made up in an empty packet supplementing mode, empty packets are correspondingly filtered out at the demodulation end, and it is guaranteed that all data transmitted by a synchronous interface is normal data.

Description

technical field [0001] The invention relates to the technical field of satellite communication, in particular to a satellite modem synchronous interface data processing system and a data processing method. Background technique [0002] V.35 is often used to support remote high-speed synchronous interfaces between DTE and different types of data service unit (DSU) connections of digital transmission facilities. It is often used in packet switches, routers, remote bridges and gateways, etc., so V.35 is used in satellite communications It also plays a very important role in the satellite modulator. The synchronous interface of the satellite modulator is of practical significance for reducing the number of devices in the application and increasing the stability of the system. [0003] Commonly used satellite modems support information rates from 2.4kbps to over 10Mbps. Different information rates require input and output data streams of corresponding rates from V.35, which requi...

AI Technical Summary

Problems solved by technology

[0005] Since the V.35 working clock and the read / write rate of the modem will not be strictly in the same frequency and phase, there will always be a certain error. After a certain period of time, the FIFO will read empty or overflow, resulting in synchronous interface out of sync or bit error.

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