Reading calibration method of memory controller, computer device and readable storage medium

Abstract

The invention provides a reading calibration method of a memory controller, a computer device and a readable storage medium, and the reading calibration method comprises the following steps: obtaining an available delay range DRAB by adopting different VREF levels, delay of a DQSB signal and delay of a DQS signal, finding a maximum group {DRAm and DRBm} in the available delay range DRAB, setting a preferable VREF level corresponding to the DRAm and the DRBm as VREFm, if the DRAm is not equal to the DRBm, adjusting the DT value of the CK duty ratio until DRAm is equal to DRBm, obtaining the optimal DTn, VREFmn, DRAmn and DRBmn, completing all calibration steps, and enabling subsequent data reading to perform reading operation on data of memory particles according to the optimal value by utilizing the best duty ratio calibration effect and the maximum sampling margin.

Description

technical field [0001] The invention relates to the technical field of DDR memory controllers, in particular to a method for reading and calibrating a DDR memory controller, a computer device and a readable storage medium. Background technique [0002] In the receiving circuit of the DDR memory controller, the data signal (DQ) sent by the particle will be compared with the internal reference decision level (VREF), and a "1" (DQ>VREF) or "0" (DQ<VREF) will be judged , and then the data sampling signal (DQS / DQSB) sent by the particle samples the result after the judgment, and then obtains the input data. [0003] Since the DDR data transmission adopts the structure of simultaneous sampling on the rising edge and the falling edge, the transmitted DQ and DQS / DQSB signal duty cycle error will seriously affect the size of the data sampling window, which will easily lead to data sampling error. During the data transmission process, as follows Duty cycle errors may exist in s...

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Problems solved by technology

[0003] Since the DDR data transmission adopts the structure of simultaneous sampling on the rising edge and the falling edge, the transmitted DQ and DQS / DQSB signal duty cycle error will seriously affect the size of the data sampling window, which will easily lead to data sampling error. During the data transmission process, as follows Duty cycle errors may exist in several situations, affecting the accuracy of data sampling:

[0004] 1. There is a duty cycle error in the DQ of the particle output;

[0005] 2. The DQS / DQSB of the particle output has a duty cycle error;

[0006] 3. The selection of the internal reference judgment level is unreasonable, resulting in a duty cycle error in the judgment result

[0007] The above three situations may lead to a decrease in the sampling margin of DQ, resulting in data reception errors

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