Verification method and verification system of chip monitor module based on UVM

Abstract

The invention provides a verification method and verification system of a chip monitor module based on a UVM. The method comprises the steps of transmitting a bus protocol data packet (namely a bus port signal) to a tested chip monitor module and a reference model module at the same time, and collecting calculation results returned by the chip monitor module and the reference model module; and comparing whether the two calculation results are the same or not so as to judge whether the behavior of the detected object (chip monitor module) is correct or not. The UVM randomization verification method adopted in the embodiment of the invention belongs to module-level verification, parameterization of verification is ensured, the problems of project inheritance and module change among different projects can be solved, and comprehensive verification can be ensured.

Description

technical field [0001] The present application relates to the technical field of chip monitor modules, in particular, to a verification method and verification system for a UVM-based chip monitor module. Background technique [0002] As the chip design becomes more and more complex, there are more and more BUGs in the chip design. After the chip is taped out, if the system is stuck and the CPU cannot work normally, the reserved debugging interface needs to access the system status. Some monitoring Then the monitor module appears, such as the DBG MNR module (DEBUG BUS MONITOR, bus debug monitor module). If the DBG MNR module itself has a BUG, ​​it will cause great difficulties for later chip-level debugging. Therefore, the verification of the DBG MNR module is also an essential link. [0003] The verification of the DBR MNR module belongs to the IP (module) level verification. For different projects, the module may need to be upgraded or its characteristics changed. However...

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Problems solved by technology

[0004] The purpose of the embodiment of the present application is to provide a UVM-based chip monitor module verification method and verification system to solve the problem of using direct test cases for verification at the system level or the full chip level, which cannot guarantee the parameterization of the verification, nor can it The problem of ensuring the convenience of project migration in the case of module changes

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