Design method for deploying and optimizing operator library on FPGA and DSP

Abstract

The invention discloses a design method for deploying and an optimizing operator library on an FPGA and a DSP. The method comprises the following steps: designing an underlying hardware operator library corresponding to an operator library of a high-level deep learning framework, and abstractly packaging operators in a lightweight network to form a fusion operator library; packaging the fusion operator library into a parallel operator library with hardware characteristics by adopting a preset segmentation strategy according to the fusion operator library in combination with computing resources of hardware; and combining the parallel operator library with a rearrangement strategy. According to the method, technical support is provided for quickly completing deployment and optimization of the deep learning network on resource-limited side-end equipment such as the DSP and the FPGA. The core of the method is to construct an underlying deep learning operator library with high practicability and high mobility. The operator library is combined with hardware characteristics and fused with efficient strategies such as heuristic segmentation and data flow rearrangement. And the basic requirements of the neural network model on the deployment of the FPGA and the multi-core DSP can be met.

Description

technical field [0001] The present invention relates to the technical field of rapid deployment and optimization of neural networks based on the characteristics of different hardware platforms, in particular to an operator library design method for deployment and optimization on FPGA and DSP, and more specifically to a lightweight neural network-oriented An optimized operator library design method for rapid deployment on FPGA and DSP. Background technique [0002] In recent years, deep learning has developed rapidly in image recognition, natural language processing, speech recognition and other fields and has shown amazing capabilities. There are more and more requirements for the deployment of deep learning models in various fields, especially in aerospace, autonomous driving and other industrial and manufacturing fields, which require higher real-time performance of deep learning algorithm deployment, but are limited by deep learning. The parameters of the network model a...

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Problems solved by technology

[0008] The purpose of the present invention is to propose an optimized operator library design method deployed on FPGA and DSP in order to solve the shortcomings of the above-mentioned prior art, which can solve the problem that the operators in the existing deep learning framework are too high-level and difficult to apply To the problem of edge hardware devices; to solve the problem that the fusion operator library is difficult to achieve efficient parallel computing, and to solve the problem of excessive number of fine-grained operator memory accesses and limited hardware storage resources

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