Memory, reading method thereof and memory system

A memory and reading reference voltage technology, applied in the semiconductor field, can solve the problems of misreading, voltage reduction, affecting the normal reading of the memory, etc., to reduce the occupied area, ensure normal reading, and reduce the probability of misreading. Effect

Pending Publication Date: 2022-01-11
YANGTZE MEMORY TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the read voltage generated by the peripheral circuit may decrease during the process of transmission to multiple drive circuits along the metal wiring, resulting in a voltage drop (IR drop), resulting in a decrease in the voltage that drives the storage plane or memory block to perform read operations, affecting memory Normal reading, even misreading

Method used

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  • Memory, reading method thereof and memory system
  • Memory, reading method thereof and memory system
  • Memory, reading method thereof and memory system

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Embodiment Construction

[0065] The technical solution of the present disclosure will be further elaborated below in conjunction with the drawings and embodiments. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0066] In the following paragraphs, the present disclosure is described more specifically by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will be more apparent from the following description and claims. It should be noted that all the drawings are in very simplified form and use inaccurate scales, which are only used to facilitate and clearly assist the purpose of...

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Abstract

The embodiment of the invention discloses a memory, a reading method thereof and a memory system. The memory includes: a memory cell array and a peripheral circuit coupled with the memory cell array and comprising a plurality of driving circuits, a voltage generation circuit used for generating a target reading reference voltage, a driving line arranged between the voltage generation circuit and the plurality of driving circuits and used for providing a target read reference voltage to the plurality of driving circuits, and a sensing line having one end coupled to the voltage generation circuit, the other end coupled to coupling nodes of the driving line and the driving circuits, and being used for transmitting actual reading reference voltage at the positions of the coupling nodes of the driving line and the driving circuits to the voltage generation circuit; and the voltage generation circuit that is also used for adjusting the value of the target read reference voltage according to the actual read reference voltage and providing the adjusted target reference voltage to the driving circuit so as to execute read operation on the memory cell array.

Description

technical field [0001] Embodiments of the present disclosure relate to but are not limited to the field of semiconductors, and in particular, relate to a memory, a reading method thereof, and a memory system. Background technique [0002] As a non-volatile memory, NAND memory has the advantages of low cost, high capacity, and fast rewriting speed. In a NAND memory, generally peripheral circuits supply power to memory cells to implement various logic operations, such as read operations, program (write) operations, and erase operations. [0003] In the related art, the electrical connection between the peripheral circuit and the memory unit can be realized by providing metal routing. Taking the read operation as an example, the metal wiring can provide the read voltage generated by the power supply in the peripheral circuit to multiple driving circuits to drive the storage planes or memory blocks respectively electrically connected to the multiple driving circuits to perform ...

Claims

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Application Information

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IPC IPC(8): G11C5/02G11C16/26G11C16/30
CPCG11C5/02G11C16/26G11C16/30
Inventor 魏汝新
Owner YANGTZE MEMORY TECH CO LTD
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