Accelerating device and server

A technology for accelerating devices and tasks, applied in the computer field, to solve problems such as limiting data transmission bandwidth

Pending Publication Date: 2022-01-18
INSPUR BUSINESS MACHINE CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The PCIE data transmission bandwidth between CPU and GPU is only about 1/8 of the data transmission bandwidth between CPU and CPU memory. The bandwidth bottleneck of dat

Method used

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  • Accelerating device and server

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Embodiment Construction

[0028] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of this application.

[0029] The core of this application is to provide an acceleration device, in order to solve the data transmission bandwidth bottleneck problem due to the bidirectional PCIE bus bandwidth of 64GB / s in the existing CPU+GPU architecture.

[0030] In order to enable those skilled in the art to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the drawings and specific implem...

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Abstract

The invention discloses an acceleration device, and relates to the field of computers, the acceleration device is applied to a CPU, the acceleration device comprises a GPU controller, a GPU and an IB exchange interface, wherein the GPU controller is connected with the GPU through an NVLink bus, the GPU controller is connected with the IB exchange interface through an IB bus, the CPU can transmit a data task needing to be processed to the GPU controller through the IB exchange interface via the IB bus, the GPU controller transmits the data task to the GPU through the NVLink bus for data processing. The GPU controller can achieve conversion between an IB protocol and an NVLink protocol, the interconnection architecture effectively solves the problem of data transmission bandwidth bottleneck of 64GB/s of bidirectional PCIE bus bandwidth in an existing CPU+GPU architecture, and data is transmitted and exchanged between a CPU memory and a GPU memory to achieve bandwidth balance.

Description

technical field [0001] The present application relates to the computer field, in particular to an acceleration device applied to a CPU of a server. Background technique [0002] The rapid increase in the amount of information in modern society has continuously increased the computing power requirements of server hardware, requiring servers to have powerful floating-point operations, matrix operations, and large-scale parallel computing capabilities, while the architecture of the central processing unit (hereinafter referred to as CPU) itself determines It is more suitable for general computing, but the computing efficiency is low. Graphics processing units (hereinafter referred to as GPUs) make up for the disadvantages of general-purpose CPUs in floating-point operations, matrix operations, and large-scale parallel computing. The current heterogeneous computing architecture of general-purpose CPU+GPU is an efficient solution for processing large amounts of data processing op...

Claims

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Application Information

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IPC IPC(8): G06F15/163G06F13/38G06F13/42
CPCG06F15/163G06F13/385G06F13/4282G06F2213/0026
Inventor 白秀杨叶丰华
Owner INSPUR BUSINESS MACHINE CO LTD
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