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Current source circuit

A technology of current source and power supply voltage, applied in the field of circuits, can solve problems such as instant start-up interference, and achieve the effect of reducing switching jitter

Pending Publication Date: 2022-02-08
PUYA SEMICON SHANGHAI CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Instantaneous Interference at Start-up in the Existing Current Source Circuit Structure

Method used

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Examples

Experimental program
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Effect test

Embodiment 1

[0046] One embodiment of the present invention, a current source circuit, comprising:

[0047] A power supply voltage input circuit for inputting a power supply voltage;

[0048] The power supply voltage anti-shake circuit is connected with the power supply voltage input circuit; the power supply voltage anti-shake circuit includes:

[0049] The first intrinsic NMOS transistor NA2, the first enhanced NMOS transistor NM1, the second enhanced NMOS transistor NM2, the third enhanced NMOS transistor NM4, the fourth enhanced NMOS transistor NM5, and the fifth enhanced NMOS transistor NM6.

[0050] The third enhanced NMOS transistor NM4 is connected to the first enhanced NMOS transistor NM1 and the second enhanced NMOS transistor NM2; the drain of the third enhanced NMOS transistor NM4 is connected to the third enhanced NMOS transistor NM4 The source of the transistor NM4 is connected; the third enhanced NMOS transistor NM4 is connected to the power supply voltage.

[0051] The so...

Embodiment 2

[0059] Based on the above embodiments, the current source circuit in this embodiment, such as figure 2 shown, also includes:

[0060] The first PMOS transistor PM2; the source of the first PMOS transistor PM2 is connected to the power supply voltage input circuit; the gate of the first PMOS transistor PM2 is connected to the drain of the second enhanced NMOS transistor NM2 Connect to the current output port of the current source.

[0061] The gate of the first intrinsic NMOS transistor NA2 is connected to the power supply voltage input circuit, the gate of the second enhanced NMOS transistor NM2, and the gate of the third enhanced NMOS transistor NM4; The drain of the first intrinsic NMOS transistor NA2 is connected to the drain of the first PMOS transistor PM2 and the drain of the second enhancement NMOS transistor NM2 .

[0062] The drain of the first enhanced NMOS transistor NM1 is connected to the source of the third enhanced NMOS transistor NM4; the source of the first...

Embodiment 3

[0073] Based on the above-mentioned embodiment, in the current source circuit in this embodiment, as figure 2 As shown, the power supply voltage input circuit includes:

[0074] The second PMOS transistor PM1, the second intrinsic NMOS transistor NA1, and the second resistor R0.

[0075] The source of the second PMOS transistor PM1 is connected to the source of the first PMOS transistor PM2; the drain of the second PMOS transistor PM1 is connected to the drain of the second intrinsic NMOS transistor NA1.

[0076] The drain of the second intrinsic NMOS transistor NA1 is also connected to the gate of the second intrinsic NMOS transistor NA1; the source of the second intrinsic NMOS transistor NA1 is connected to a port for inputting a reference voltage; The gate of the second intrinsic NMOS transistor NA1 is connected to the gate of the first intrinsic NMOS transistor NA2; the source of the second intrinsic NMOS transistor NA1 is also connected to the gate of the second resisto...

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PUM

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Abstract

The invention relates to the technical field of circuits, and provides a current source circuit which comprises a power voltage input circuit for inputting power voltage; a power voltage anti-shake circuit is connected with the power voltage input circuit; the power voltage anti-shake circuit comprises a third enhanced NMOS (N-channel Metal Oxide Semiconductor) tube which is connected with a first enhanced NMOS tube and a second enhanced NMOS tube; the drain electrode of the third enhanced NMOS tube is connected with the source electrode of the third enhanced NMOS tube; the third enhanced NMOS tube is connected with a power voltage; the source electrode of a first intrinsic NMOS tube, the drain electrode of a fifth enhanced NMOS tube and the drain electrode of a fourth enhanced NMOS tube are connected to a first node; the source electrode of the second enhanced NMOS tube, the drain electrode of the third enhanced NMOS tube, the source electrode of the third enhanced NMOS tube and the source electrode of the fifth enhanced NMOS tube are connected to a second node; when the standby mode is switched to the normal working mode, the fifth enhanced NMOS tube is turned on, and the voltage of the second node is increased for pre-charging. According to the invention, the stable time and the jitter amplitude of the voltage bias of the output current source during circuit mode switching can be effectively reduced.

Description

technical field [0001] The invention relates to the technical field of circuits, in particular to a current source circuit. Background technique [0002] The existing current source circuit has only one working mode - Active mode, such as figure 1 shown. In Active mode, the gate voltage (Vg5) of the NMOS transistor (NM5) is connected to VDD, and BGRBlock outputs VREF. At this time, the current source circuit can work normally, and the subsequent output is proportional to the operational amplifier circuit. The output current reference is Vref / R1, the actual output size can be adjusted by the mirror ratio. In the existing current source circuit structure, there is a problem of transient interference at start-up. Contents of the invention [0003] The object of the present invention is to provide a current source circuit through which the above problems can be solved. [0004] The technical scheme provided by the invention is as follows: [0005] A current source circui...

Claims

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Application Information

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IPC IPC(8): G05F1/56
CPCG05F1/561Y02B70/10
Inventor 李兆桂易鹏高会阁
Owner PUYA SEMICON SHANGHAI CO LTD
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