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Clock monitoring circuit

A technology for monitoring circuits and clocks, applied to electrical components, generating electrical pulses, monitoring pulse chain modes, etc., can solve problems such as clock measurement errors

Pending Publication Date: 2022-02-22
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the method of counting the divided clock may have many errors in the measurement compared to the method of directly counting the clock generated by the ring oscillator

Method used

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Embodiment Construction

[0036] Various examples of the present disclosure are described in more detail below with reference to the accompanying drawings. However, the aspects and features of the present technology can be implemented in different ways to form other embodiments including variations of any of the disclosed embodiments. Accordingly, the disclosed technology is not to be construed as limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey this disclosure to those skilled in the art to which this technology pertains. Throughout the disclosure, like reference numerals refer to like parts in the various figures and examples of this disclosure. Note that references to "an embodiment," "another embodiment," etc. do not necessarily mean a single embodiment, and that different references to any such phrase are not necessarily to the same embodiment(s).

[0037] It will be understood...

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Abstract

The present disclosure relates to a monitoring circuit comprising a clock generator adapted to generate a first clock having a first target frequency; a code generator suitable for generating an output code by changing a value of the input code in response to an input clock, receiving a feedback signal associated with the output code, and changing the value of the input code by performing a setting operation in a first mode and an inverse setting operation in a second mode; and an operation controller suitable for transmitting the first clock and the start code as an input clock and an input code when entering the first mode, setting the output code as a count code when exiting the first mode, transmitting the second clock and the count code as the input clock and the input code when entering the second mode, and counting the number of triggers of the second clock in the second mode until the output code has the same value as the value of the start code to generate the monitoring information.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2020-0103792 filed on August 19, 2020, which is hereby incorporated by reference in its entirety. technical field [0003] Embodiments relate to a semiconductor design technique, and more particularly, to a clock monitoring circuit used in a semiconductor device. Background technique [0004] As VLSI process technology improves, semiconductor circuits are more affected by process, voltage, and temperature (PVT) variations. [0005] In particular, a clock generating circuit such as a ring oscillator for generating a clock within a semiconductor device may be significantly affected by such PVT variation. That is, in order to generate a clock set to a specific target frequency, a ring oscillator included in a semiconductor device may generate a clock having a significant frequency difference from the specific target frequency according to PVT variatio...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/14
CPCG06F1/14H03K5/133H03K2005/0015G06F1/06H03K5/19H03K3/011H03K3/0315H03L7/00
Inventor 裵相民
Owner SK HYNIX INC
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