CPU forced shutdown control method and circuit
A shutdown control and circuit technology, applied in the computer field, can solve problems such as inconvenient startup, and achieve the effect of small workload and low cost
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Embodiment 1
[0067] The embodiment of the present application discloses a CPU forced shutdown control method, including the following steps:
[0068] S100: Detect a forced shutdown action.
[0069] S200: After detecting the forced shutdown action, reset the RSMRST signal pin of the Intel apollo lake processor.
[0070] Specifically, refer to image 3 , one end of the switch button (SW) is connected to the CPU and the power supply VCC, and the other end of the switch button is grounded. When the switch button is not pressed, the potential at the connection point between the switch button and the CPU is high. When pressed When the power button is turned on, the potential at the connection point between the power button and the CPU is at a low level, and the low level is a key signal.
[0071] When it is detected that the duration of the key signal reaches the preset time, and it is detected that the SLEEP_S4 signal pin and the SOC_PWROK pin of the CPU are at a low level, it is determined t...
Embodiment 2
[0077] The embodiment of the present application discloses a CPU forced shutdown control circuit. refer to image 3 and Figure 5 The CPU forced shutdown control circuit includes a monitoring control circuit connected to the switch button and the CPU, and the monitoring control circuit includes a timing control module 1 and a reset module 2 . Timing control module 1 is connected with switch button, CPU, is used for monitoring button signal, and when the duration of button signal reaches preset time, output control signal, wherein, CPU is Intel apollo lake processor. The reset module 2 is connected with the timing control module 1 and the CPU, and is used to reset the RSMRST signal pin of the CPU when the control signal is received and the SLEEP_S4 signal pin and the SOC_PWROK pin of the CPU are detected to be at low level. Among them, the SOC_PWROK pin of the CPU is used to detect the SYSPWRGD signal.
[0078] Optionally, the timing control module 1 includes a first switch ...
Embodiment 3
[0104] refer to Figure 6 The difference between this embodiment and Embodiment 2 is that the timing control module 1 uses a timing chip U1, the input end of the timing chip U1 is connected to the fourth resistor R4, and the output end of the timing chip U1 is connected to the gate of the second MOS transistor Q2. pole connection.
[0105] The implementation principle of embodiment 3 is: press the switch button, the input terminal of the timing chip U1 becomes low level, the timing chip U1 starts timing, after the timing time reaches the preset time, the output terminal of the timing chip U1 outputs a high voltage. level, the second MOS transistor Q2 is turned on.
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