Method and device for realizing command scheduling, computer storage medium and terminal

Abstract

The invention discloses a method and device for realizing command scheduling, a computer storage medium and a terminal, and the method comprises the steps: determining whether a first position for inserting a first command exists in a command queue or not when a dynamic random access memory (DRAM) receives the first command; when the first position exists, determining whether the first position passes consistency conflict check or not; inserting a first command into the first location passing the consistency conflict check; wherein the first command comprises a read command or a write command. According to the embodiment of the invention, under the condition that the command queue is not subjected to read-write grouping, the newly received first command is subjected to the consistency conflict check and then is subjected to insertion processing, so that the read-write performance of a system on chip (SOC) is improved.

Description

technical field [0001] This article relates to, but is not limited to, SoC technology, especially a method, device, computer storage medium, and terminal for implementing command scheduling. Background technique [0002] With the increasing scale of the system on chip (SOC), more and more modules such as central processing unit (CPU) and data processing unit (DPU) are integrated in the SOC; the efficiency of the system to execute the DRAM cache of each module, It will directly affect the overall performance of the SOC. [0003] The dynamic random access memory (DRAM) controller is the basic component for parsing and processing SOC bus commands. It mainly schedules read and write commands according to the read and write classification or queue rearrangement technology; among them, the read and write classification in the related art, fixed rules And the queue scheduling strategy of strongly coupled logic; the complexity of the current scheduling strategy is getting higher an...

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Problems solved by technology

[0003] Dynamic random access memory (DRAM) controller is the basic component of parsing and processing SOC bus order, mainly carries out the dispatching of reading and writing command according to reading and writing classification or queue rearrangement technology; Wherein, the reading and writing classification in related technology, fixed rule And the queue scheduling strategy of strong coupling logic; the complexity of the current scheduling strategy is getting higher and higher, and there are problems such as low flexibility, tight logic coupling and poor compatibility; it has become a major problem in the design of current DRAM controllers

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