Phase locked loop with dual input reference and dynamic bandwidth control

Abstract

Systems and methods for improved performance of phase-locked loop-based clock generators, particularly in the context of wireless audio, are disclosed herein. The PLL clock generator includes: a PLL core configured to receive a module reference clock provided by the communication module and generate a subsystem data clock corresponding to a module data clock of the communication module; and a data clock tracker module configured to receive the module data and the subsystem data clock and determine a corresponding data clock correction factor. In this way, the bandwidth of the PLL core can be dynamically changed, thereby achieving fast and very precise stabilization. The PLL core may use a low jitter frequency reference for the phase detector while using a synchronized and easily jitter audio sampling clock to ensure that the average frequency of the PLL core tracks the audio sampling clock.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS [0002] This application claims priority under 35 USC § 119(e) to and the benefit of US Provisional Patent Application No. 63 / 126,439, filed on December 16, 2020, which is incorporated herein by reference in its entirety. technical field [0003] According to one or more embodiments, the present disclosure relates generally to phase locked loops (PLLs), and more particularly, for example, to systems and methods for generating stable clock signals using PLLs. Background technique [0004] Many modern devices, such as laptops, tablets, MP3 players, smart phones, and audio receivers, provide wireless source, speaker, and / or headset connectivity. A stable clock in the audio subsystem of such a device may be difficult to achieve, especially when one or more of the wirelessly interconnected devices are portable and the wireless communication link may be degraded or degraded due to interference and / or distance. The audio subsystem ma...

AI Technical Summary

Problems solved by technology

A stable clock in the audio subsystem of such a device may be difficult to achieve, especially when one or more of the wireless interconnected devices is portable and the wireless communication link may degrade or drop due to interference and / or distance

The audio subsystem may employ a phase-locked loop (PLL) based clock generator in an attempt to provide a stable clock for the audio subsystem, but conventional PLL based clock generators may "lose lock" and become cause the audio subsystem to suffer from audible audio capture and / or reproduction errors and / or other operational errors, for example, or they incorporate mitigation mechanisms that significantly increase system complexity and power consumption

Images