Memory module and memory bus signal processing method

Abstract

The invention discloses a memory module. The memory module comprises a buffer and a plurality of memory particles, the buffer is connected to the processor by a first memory bus while connected to the plurality of memory particles by a second memory bus. Wherein the first memory bus and the second memory bus support the same standard. The buffer is used for converting a signal on the first memory bus into a signal on the second memory bus. Wherein the data rate of the signal on the first memory bus is different from the data rate of the signal on the second memory bus. Through the technical scheme, the problem that the memory particles are not matched with the highest data rate of the signal supported by the memory bus of the processor can be effectively solved.

Description

technical field [0001] The present application relates to computer systems, and in particular, to a memory module, a memory bus signal processing method, and a computer system. Background technique [0002] Products of the double data rate synchronous dynamic random access memory (DDR SDRAM) standard have been widely used in computer systems. At present, the DDR SDRAM standard has evolved to the DDR5 standard, with a data rate of up to 6400 mega-transfer per second (MT / s). [0003] The introduction of DDR5 standard memory particle products is slower than the introduction of DDR5 standard processor products. For example, the memory bus of processor products that support the DDR5 standard now supports signals with a data rate of up to 6400MT / s, but the memory chips of the DDR5 standard currently only support signals up to 3200MT / s. Such memory particles cannot fully utilize the performance advantages of the processor's memory bus in a computer system. SUMMARY OF THE INVENT...

AI Technical Summary

Problems solved by technology

The signal of the memory bus of the processor is converted into the signal on the memory bus of the memory granule, which can effectively solve the problem of the mismatch of the highest data rate of the signal supported by the memory bus of the memory granule and the signal supported by the memory bus of the processor.

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