Simulation method and device, power line topology network, test circuit and storage medium

A technology of topology network and simulation method, applied in the fields of power line topology network, test circuit and storage medium, device, and simulation method, can solve the problems of long simulation time and slow simulation speed, so as to improve the simulation speed, realize the simulation accuracy and Simulation speed and the effect of improving simulation accuracy

Pending Publication Date: 2022-07-29
CHANGXIN MEMORY TECH INC
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Problems solved by technology

[0003] In the above simulation process, on the one hand, repeated verification is required, and on the other hand, the simulation speed is very s

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  • Simulation method and device, power line topology network, test circuit and storage medium
  • Simulation method and device, power line topology network, test circuit and storage medium
  • Simulation method and device, power line topology network, test circuit and storage medium

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[0066] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the accompanying drawings in the present application. Obviously, the described embodiments are part of the embodiments of the present application. , not all examples. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0067] In the existing integrated circuit design process, in the post-simulation, if the scale of the post-simulation netlist including the parasitic capacitance and resistance of the power line layout is very large, the simulation time is very long, which cannot meet the actual project requirements. However, if the power line parasitic components are not included in the post-simul...

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Abstract

The invention provides a simulation method and device, a power line topology network, a test circuit and a storage medium. The method comprises the steps that a power line topology network is generated according to a power line layout, the power line topology network comprises a plurality of first-layer metal wires which are transversely arranged, a plurality of second-layer metal wires which are longitudinally arranged, power supply child nodes and parasitic elements, and the parasitic elements are located between the two power supply child nodes; the minimum voltage of a power input node of each circuit module in a circuit corresponding to the power line topology network is determined, the power input node is one of power child nodes in each circuit module, and time sequence simulation is carried out according to the minimum voltage of the power input node of each circuit module and the integrated circuit post-simulation circuit netlist. Therefore, the influence of the voltage drop of the power line on the time sequence parameters of the integrated circuit can be evaluated through normal time sequence simulation, and the simulation precision and the simulation speed are improved.

Description

technical field [0001] The present application relates to the technical field of integrated circuits, and in particular, to a simulation method, an apparatus, a power line topology network, a test circuit and a storage medium. Background technique [0002] At present, in integrated circuit design, the design process of integrated circuit design includes circuit design and pre-simulation, layout design and post-simulation and other processes. Among them, the circuit design is specifically to complete the circuit design according to the circuit function, and the pre-simulation is specifically to simulate the circuit function, including the simulation of parameters such as power consumption, current, voltage, temperature, and input and output characteristics. The pre-simulation does not consider the influence of the parasitic capacitance and resistance generated by the metal wires in the circuit. After the layout design is completed, the parasitic capacitance and resistance are...

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Application Information

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IPC IPC(8): G06F30/3947G06F30/20G06F115/10
CPCG06F30/3947G06F30/20G06F2115/10G06F30/33
Inventor 杜涛徐帆
Owner CHANGXIN MEMORY TECH INC
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