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Network-on-chip design method for distributed parallel operation algorithm

An on-chip network and design method technology, applied in the field of computer algorithms, can solve the problems of network consumption, low network communication efficiency, low clock frequency, etc., and achieve the effect of reducing total delay, reducing the use of on-chip resources, and improving real-time performance.

Pending Publication Date: 2022-08-02
YANGTZE DELTA REGION INST OF UNIV OF ELECTRONICS SCI & TECH OF CHINE HUZHOU
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Problems solved by technology

[0013] It solves the low clock frequency caused by the excessive bus interconnection combinatorial logic delay of traditional hardware accelerators containing multiple computing units, and also solves the problem of low network communication efficiency and network hardware consumption caused by general on-chip network unicast and multicast sharing a network To solve the problem of many resources, it provides an on-chip network design method for distributed parallel computing algorithms

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  • Network-on-chip design method for distributed parallel operation algorithm
  • Network-on-chip design method for distributed parallel operation algorithm
  • Network-on-chip design method for distributed parallel operation algorithm

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Embodiment Construction

[0030] A kind of network-on-a-chip design method for distributed parallel computing algorithms of the present invention will be further described with reference to the accompanying drawings, and the present invention will be further described in detail below with reference to the embodiments:

[0031] An on-chip network design method oriented to distributed parallel computing algorithms. According to the distributed parallel computing algorithm of the on-chip network, the on-chip network is divided into two layers, including a unicast network and a multicast network. The unicast network realizes the The point-to-point propagation of the computing node transmits the independent computing data required by each computing node to each computing node in the form of unicast; the multicast network is a customized multicast network for distributed parallel computing algorithms, which is used to transmit to all computing nodes. There is a shared operation data, and the efficient transmi...

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Abstract

The invention relates to the technical field of computer algorithms, in particular to a network-on-chip design method oriented to a distributed parallel computing algorithm, a network-on-chip is divided into two layers including a unicast network and a multicast network according to the distributed parallel computing algorithm of the network-on-chip, the unicast network realizes point-to-point propagation among nodes, and the multicast network realizes point-to-point propagation among nodes. Independent operation data required by each operation node is transmitted to each operation node in a unicast mode; the multicast network is a customized multicast network oriented to a distributed parallel computing algorithm and is used for transmitting common computing data to all computing nodes, efficient transmission of data packets in the network is achieved through combination of the unicast network and the multicast network, and efficient transmission of the data packets in the network is achieved through design of a multicast tree-shaped transmission architecture oriented to the distributed parallel computing algorithm. A bi-directional replication node or a receiving node is arranged at each operation node, and the architecture is different from the structure that each node in a traditional multicast network-on-chip is provided with a multicast sending module and a multicast receiving module, so that the use of on-chip resources is reduced to the maximum extent.

Description

technical field [0001] The invention relates to the technical field of computer algorithms, in particular to an on-chip network design method oriented to distributed parallel computing algorithms. Background technique [0002] Distributed parallel computing widely exists in various deep learning and target tracking algorithms. Distributed parallel computing can be defined as an algorithm that performs a series of operations with the same steps and has no data dependency between different computing data in the computing process and can be executed in parallel. Typical distributed operations include distance operations between two coordinate vectors, various matrix multiplications, and convolution operations in deep learning algorithms. [0003] The characteristics of distributed parallel computing are that the computing is dense and decentralized, and the operations between each data are independent. This kind of computing involves a large number of operations in today's gene...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L41/04H04L49/109H04L67/1074
CPCH04L49/109H04L41/04H04L67/1074H04L2012/5641H04L2012/5642Y02D30/70H04L49/201H04L49/3063
Inventor 黄乐天邓子阳
Owner YANGTZE DELTA REGION INST OF UNIV OF ELECTRONICS SCI & TECH OF CHINE HUZHOU
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