The present invention relates to a VDF (initial state, t), comprising: a one-way invertible function S component directly or indirectly constructing the VDF, wherein the S component is defined as an invertible function where a computation
delay of forward logic is significantly greater than that of reverse logic; a computation phase: a intermediate states, and / or F(A0, Ab)=S(A0⊕Ab, △) indirectly constructing the VDF; and a
verification phase: receiving the initial state and a+1 states, preferably completing a+1 VDF-1
verification tasks by means of parallel (a+1)*(b?b:1) S-1 logic verifications. A VDF construction with salt is preferred; the S component preferably has a structure of F(A, B)=g(A⊕B), wherein g-1 uses sparse tap design. Disclosed are proposed industrial standards VDF32 and VDF8192. The present invention achieves the effects of no initialization parameter phase (Setup);
quantum-resistant design; and entropy preservation. Disclosed related uses comprise a randomness
beacon, a portal website, a proof-of-replication, a storage service terminal, a
cloud computing terminal, two types of
blockchain systems, Token encoding and
verification, and automatic commitment opening. To support industrial implementation, further disclosed are a VDF computing apparatus, a VDF verification apparatus, a medium, and a
chip.