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NOT gate circuit

A non-gate circuit and low-level technology, applied in circuits, logic circuits with logic functions, electrical components, etc., can solve problems such as leakage current and increased power consumption of the non-gate circuit

Inactive Publication Date: 2004-12-15
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, when the received external input signal cannot be in an ideal state, for example, when the received low-level signal is 0.75 volts and 0.9 volts, which are more than 0 volts, the N-channel metal-oxide transistor 12 will be blocked. Slightly turned on to generate leakage current, so that the power consumption of this NOT gate circuit is greatly increased

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Embodiment Construction

[0020] See figure 2 , which is a block diagram of a preferred embodiment of the NOT gate circuit structure developed by the present invention to improve the defects of the prior art, except for the first N-channel metal_oxide transistor 21 (NMOS) and the P-channel metal_ In addition to the oxide transistor 22 (PMOS), a voltage drop component 23 is mainly provided between the gate of the first N-channel metal-oxide transistor and the input terminal to provide the input terminal 20 to the first A voltage drop between the gates of the N-channel metal-oxide transistor 21, thereby eliminating the first N-channel metal-oxide transistor when the input signal is at a low level (for example, between 0.75 volts and 0.9 volts) when the leakage current is generated.

[0021] See image 3 , which is a schematic diagram of a circuit example of a diode to complete the voltage drop component 23, the anode of the diode 30 is coupled to the input terminal 20, and its cathode is connected to ...

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Abstract

The present ivnention discloses a circuit structure of NOT gate, which includes an input end, a P channel MOS transistor, a first N channel MOS transistor and a voltage drop module. The input end receives the input signal, which possesses two electrical levels: high and low, and the low voltage level is larger than zero voltage. The grid electrode of the P channel MOS transistor is coupled to the input end. The source electrode is coupled to the power source. The drain electrode of the first N channel MOS transistor is coupled to the drain electrode of the P channel MOS transistor to form the output end. The source electrode of the N channel MOS transistor is coupled to the grounding point. The voltage drop module is coupled between the grid electrode of the first N channel MOS transistor and the input end, providing the lowered amplitude of voltage from the input end to the grit electrode of the N channel MOS transistor.

Description

technical field [0001] The invention relates to a NOT gate circuit structure, in particular to a NOT gate circuit structure applied in integrated circuits. Background technique [0002] See figure 1 , which is a schematic circuit diagram of a currently known CMOS NOT gate, as can be clearly seen from the figure, the NOT gate is mainly composed of an N-channel metal-oxide transistor 11 (NMOS) and a P-channel metal-oxide transistor. The object transistor 12 (PMOS) constitutes. And when the input signal is an ideal bi-level signal (for example, the low level is 0 volts and the high level is 2.5 volts), it only generates current when switching states, and does not generate any current when it is steady state . [0003] However, when the received external input signal cannot be in an ideal state, for example, when the received low-level signal is 0.75 volts and 0.9 volts, which are more than 0 volts, the N-channel metal-oxide transistor 12 will be blocked. Leakage current is ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/04H03K19/20
Inventor 黄超圣
Owner VIA TECH INC