Semiconductor device with protection circuit

A technology for protecting circuits and semiconductors, applied in semiconductor devices, electric solid state devices, semiconductor/solid state device components, etc., can solve problems such as high voltage, non-terminal breakdown, gate insulating film breakdown, etc. Effect

Inactive Publication Date: 2005-01-05
PS4 LUXCO SARL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0013] In addition, it is found that when the electrostatic voltage applied to the non-connection terminal rises, the voltage induced on the terminal is very high, and then decays rapidly. This p

Method used

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  • Semiconductor device with protection circuit
  • Semiconductor device with protection circuit
  • Semiconductor device with protection circuit

Examples

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Embodiment Construction

[0032] A preferred embodiment of the present invention will be described with reference to the accompanying drawings.

[0033] Such as figure 1 The LOC semiconductor device of an embodiment of the present invention shown in includes a semiconductor chip 10, and a plurality of pads (22 of which are shown) 11 on the semiconductor chip 10, a plurality of terminals or wires 12 ( 22 of them are shown). The four pads 11a among the pads 11 arranged on the semiconductor chip 10 are optional pads which are not electrically connected to any lead 12, and the four leads 12a among the plurality of leads 12 are not connected to any pad 11. connected. The other eighteen leads are terminals 12b.

[0034] Such as figure 1 As shown in , the non-terminal 12a is not electrically connected to any alternative pad 11a, while the terminal 12b is electrically connected to the pad 11. Non-connection terminals (leads) 12a and connection terminals 12b are sealed together with the semiconductor chip ...

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PUM

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Abstract

A lead on chip (LOC) semiconductor device or a chip on lead (COL) semiconductor device with a protection circuit. Non-connection pins are made shorter than connection pins to reduce the inductance of the non-connection pins, or to obtain a different capability of the protection circuit for non-connection pins with respect to connection pins. The time constant of the protection circuit for the non-connection pins is made longer than that of the protection circuit for the connection pins. Further, the clamping capability for the connection pins is made greater than that for another connection pin adjacent to the connection pin.

Description

technical field [0001] The present invention relates to a semiconductor integrated circuit with non-connection terminals which are neither input / output nor voltage source. Background technique [0002] In general, lead-on-chip (LOC) semiconductor devices or chip-on-lead (COL) semiconductor devices are provided with definite terminals connected to input circuits, output circuits, and voltage source circuits, as well as the aforementioned non- Terminals. Such non-connection terminals are inevitably provided for free selection especially in the case of gate arrays. [0003] In addition, the semiconductor device of LOC or COL is supported on a lead frame including terminals and non-connection terminals of bonding wires. Therefore, both the connection terminal and the non-connection terminal extend to the position where the semiconductor chip is supported. [0004] Therefore, in the semiconductor device package using the above-mentioned lead frame, the non-connection terminal ...

Claims

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Application Information

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IPC IPC(8): H01L23/495H01L23/60H01L27/02H02H9/04
CPCH01L24/45H01L2924/01082H01L2924/00014H01L2224/85399H01L23/60H01L24/48H01L2224/48247H01L24/06H01L2224/45099H01L2224/04042H01L2924/13091H01L2924/14H01L2924/01033H01L24/49H02H9/046H01L2224/05599H01L2924/19041H01L23/4951H01L2224/06136H01L2224/49171H01L2924/30107H01L27/0248H01L2224/05554H01L2924/1305H01L2924/12036H01L2224/4826H01L2924/00H01L23/58
Inventor 藤井威男成田薰堀口洋子
Owner PS4 LUXCO SARL
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