32 results about "Lead on chip" patented technology

A thermally enhanced, chip-scale, Lead-on-Chip (“LOC”) semiconductor package includes a substrate having a plurality of metal lead fingers in it. A semiconductor chip having an active surface with a plurality of ground, power, and signal connection pads thereon is mounted on an upper surface of the substrate in a flip-chip electrical connection with the lead fingers. A plurality of the ground and/or the power connection pads on the chip are located in a central region thereof. Corresponding metal grounding and/or power lands are formed in the substrate at positions corresponding to the centrally located ground and/or power pads on the chip. The ground and power pads on the chip are connected to corresponding ones of the grounding and power lands in the substrate in a flip-chip connection, and a lower surface of the lands is exposed to the environment through a lower surface of the semiconductor package for connection to an external heat sink. The lands can be connected to selected ones of the lead fingers, and/or combined with one another for even greater thermal and electrical conductivity.

A thermally enhanced, chip-scale, Lead-on Chip (“LOC”) semiconductor packages includes a substrate having a plurality of metal lead fingers in it. A semiconductor chip having an active surface with a plurality of ground, power, and signal connection pads thereon is mounted on an upper surface of the substrate in a flip-chip electrical connection with the lead fingers. A plurality of the ground and/or the power connection pads on the chip are located in a central region thereof. Corresponding metal grounding and/or power lands are formed in the substrate at positions corresponding to the centrally located ground and/or power pads on the chip. The ground and power pads on the chip are connected to corresponding ones of the grounding and power lands in the substrate in a flip-chip connection, and a lower surface of the lands is exposed to the environment through a lower surface of the semiconductor package for connection to an external heat sink. The lands can be connected to selected ones of the lead fingers, and/or combined with one another for even greater thermal and electrical conductivity.

A magnetic field sensor includes a lead frame, a semiconductor die supporting a magnetic field sensing element, a non-conductive mold material enclosing the die and a portion of the lead frame, a ferromagnetic mold material secured to the non-conductive mold material and a securing mechanism to securely engage the mold materials. The ferromagnetic mold material may comprise a soft ferromagnetic material to form a concentrator or a hard ferromagnetic material to form a bias magnet. The ferromagnetic mold material may be tapered and includes a non-contiguous central region, as may be an aperture or may contain the non-conductive mold material or an overmold material. Further embodiments include die up, lead on chip, and flip-chip arrangements, wafer level techniques to form the concentrator or bias magnet, integrated components, such as capacitors, on the lead frame, and a bias magnet with one or more channels to facilitate overmolding.

A die bonding apparatus includes: a lead frame supply station for accommodating a plurality of lead frames; a frame transferring device for picking up the lead frame and transferring it to an Ag epoxy application table or to a traveling rail; a frame fixing station for fixing the lead frame to the Ag epoxy application table by suction power of a vacuum pump or moving it back and forth through actuation of a motor; an Ag epoxy supply station for ejecting a predetermined amount of Ag epoxy through a nozzle to the top surface of the lead frame; a moving device for moving the lead frame forward on the traveling rail; a preheating station for receiving the lead frame into a magazine and preheating it; a wafer placement station for transferring wafers sequentially supplied from a wafer supply station to a predetermined location through rotation; a die transferring device for picking up a die and transferring it to a work site for die bonding; a die bonding station for precisely bonding the die to a site where a tape is stuck or Ag epoxy is applied in the lead frame according to lead on chip (LOC) or normal feature of the lead frame; and a stocker for accommodating the lead frame into an internal magazine.

A magnetic field sensor includes a lead frame having a plurality of leads, at least two of which have a connection portion and a die attach portion. A semiconductor die is attached to the die attach portion of the at least two leads. The sensor further includes at least one wire bond coupled between the die and a first surface of the lead frame. The die is attached to a second, opposing surface of the lead frame in a lead on chip configuration. In some embodiments, at least one passive component is attached to the die attach portion of at least two leads.

A semiconductor package, and a method for fabricating the package are provided. The package includes a plastic body, and a pair of stacked semiconductor dice encapsulated in the plastic body, and wire bonded to separate leadframe segments. A first leadframe segment includes lead fingers configured to support a first semiconductor die of the stacked pair, and to form terminal leads of the package. A second leadframe segment is attached to the first leadframe segment, and includes lead fingers that support a second semiconductor die of the stacked pair. The lead fingers of the second leadframe are in physical and electrical contact with the leadfingers of the first leadframe. In addition, tip portions of the lead fingers of the first leadframe segment are staggered relative to tip portions of the lead fingers of the second leadframe segment to provide space for bond wires. The lead fingers support the dice during encapsulation, and also provide a heat conductive path for transferring heat from the dice during operation. The package can be constructed using lead-on-chip leadframes and conventional semiconductor packaging equipment.

A thermally enhanced, chip-scale, Lead-on-Chip (“LOC”) semiconductor package includes a substrate having a plurality of metal lead fingers in it. A semiconductor chip having an active surface with a plurality of ground, power, and signal connection pads thereon is mounted on an upper surface of the substrate in a flip-chip electrical connection with the lead fingers. A plurality of the ground and/or the power connection pads on the chip are located in a central region thereof. Corresponding metal grounding and/or power lands are formed in the substrate at positions corresponding to the centrally located ground and/or power pads on the chip. The ground and power pads on the chip are connected to corresponding ones of the grounding and power lands in the substrate in a flip-chip connection, and a lower surface of the lands is exposed to the environment through a lower surface of the semiconductor package for connection to an external heat sink. The lands can be connected to selected ones of the lead fingers, and/or combined with one another for even greater thermal and electrical conductivity.

A packaging assembly (30), such as a ball grid array package, is formed which distributes power across an interior region of an integrated circuit die (52) by using an encapsulated patterned leadframe conductor (59) that is disposed over the die (52) and bonded to a plurality of bonding pads (45) formed in a BGA carrier substrate (42) and in the interior die region, thereby electrically coupling the interior die region to an externally provided reference voltage.

A chip-stacked package structure comprises a lead frame, a first chip, and a second chip. The led frame is composed of a plurality of inner leads and a plurality of outer leads. The plurality of inner leads comprises a plurality of first inner leads in parallel and a plurality of second inner leads in parallel, wherein the ends of first inner leads and the ends of second inner leads are arranged in rows facing each other at a distance. The active surface of first chip is fixedly connected to the lower surface of first inner leads and second inner leads via a first adhesive layer. A plurality of metal pads is provided near the central area of the active surface of first chip and is exposed. A second adhesive layer is formed on the back surface of second chip for fixedly connecting the back surface of second chip and the upper surface of first inner leads and second inner leads. The gap formed by the thickness of second adhesive layer prevents the bonding wires connecting the first chip from contacting the back surface of second chip.

A multi-chip semiconductor package structure. The structure includes two chips and two lead frames. The leads on one of the lead frames have inner leads at one end and joint sections at the other end. The joint sections are connected with another lead frame. Both lead frames use a common set of external leads. The two chips and two lead frames are joined together forming a lead-on-chip structure with the two chips facing each other back-to-back. The assembly except the external leads is enclosed by packaging material.

Provided are semiconductor devices and methods for configuring lead frames and/or device bonding pads to provide for the independent adjustment of the electrical characteristics of both fixed voltage lines, e.g., V_dd and V_ss, and the signal lines, e.g., command, clock, data and address. In particular, the invention provides for adjusting the relative sizing of leads corresponding to fixed voltage lines and signal lines for increasing the relative capacitance on the fixed voltage lines to improve their stability will reducing the noise on the signal lines. The invention may be utilized with a variety of package configurations including lead-on-chip LOC configurations, more conventional quad flat pack QFP configurations in which the leads do not extend past the perimeter of the semiconductor chip or hybrid configurations in which some leads do extend past the perimeter of the semiconductor chip and across the active surface.

A semiconductor integrated circuit device includes a semiconductor chip having a memory cell array region surrounded with a peripheral circuit region and includes a plurality of bonding pads disposed at least in one row on only one side of the semiconductor chip. The circuit device may include first leads group disposed adjacent to the bonding pad side and a second leads group disposed opposite the first leads group. The second leads group may be formed over a portion of the semiconductor chip (lead-on-chip structure). A plurality of bonding wires connect the first and second leads group with the plurality of bonding pads respectively.

A BGA package primarily includes a plurality of leads from a leadless lead frame, a chip, and a die-attaching layer. The chip is electrically connected to the leads by a plurality of bonding wires. Solder balls are disposed at the ball placing regions of the leads. Encapsulant encapsulates the chip, the die-attaching layer, and the top surfaces, the bottom surfaces, and the sides of the leads so that the ball placing regions are embedded inside the encapsulant. A plurality of cavities are formed in the encapsulant to expose the corresponding ball placing regions to resolve the solderability of the solder balls and to enhance the stability and reliability of wire bonding and solder ball placing. In one embodiment, a die-attaching layer between the chip and the leads is patterned for elastically supporting the solder balls and for wire bonding.

A BGA package primarily includes a leadless leadframe with a plurality of leads, a chip disposed on the leads, a die-attaching layer adhering to an active surface of the chip and the top surfaces of the leads, a plurality of bonding wires electrically connecting the chip to the leads, an encapsulant, and a plurality of solder balls. Each lead has a bottom surface including a wire-bonding area and a ball-placement area, moreover, a plurality of lips project from the bottom surfaces of the leads around the ball-placement areas. The encapsulant encapsulates the chip, the bonding wires, the die-attaching layer, and the top surfaces, the bottom surfaces except the ball-placement areas, and the laterals of the leads between the top surfaces and the bottom surfaces. A plurality of cavities are formed in the bottom of the encapsulant to expose the corresponding and embedded ball-placement areas. The lips have a plurality of internal sides exposed inside the cavities. The solder balls are disposed on the ball-placement areas and on the internal sides of the cavities to make the solder balls partially embedded in the corresponding cavities to offer non-planar ball pads. It is effective to resolve the solderability of the solder balls and to enhance the reliability of wire bonding and the stability of solder ball placement.

The invention discloses a semiconductor package and a manufacturing method thereof. The semiconductor package comprises a chip, chip surface protecting layers, chip bonding pads, lead on chip (LOC) tapes, pins, conducting components and resins, wherein the chip surface protecting layers are formed on the chip and cover the areas except the areas in which the chip bonding pads are about to form; the chip bonding pads are formed in the areas, which are not covered by the chip surface protecting layers, on the chip; the LOC tapes are formed on the chip surface protecting layers; the pins are formed on the LOC tapes which bond the pins and the chip surface protecting layers; the conducting components are formed on the chip bonding pads and part of the chip surface protecting layers and connect the chip bonding pads with the pins electrically; and the resins are used for packaging the components.

Used for semiconductor packing, an adhesive agent (130) is used on parts of a conductor framework (120) and on parts of a specific surface on an integrated switching circuit chip (ISCC) so as to hold the conductor framework on the ISCC. A majority of input/output contact points (112) are located on the top side of the ISCC. Independent claims are also included for the following: (A) A method for producing semiconductor packing; (B) and for a device for producing semiconductor packing.

As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

A lead on chip (LOC) semiconductor device or a chip on lead (COL) semiconductor device with a protection circuit. Non-connection pins are made shorter than connection pins to reduce the inductance of the non-connection pins, or to obtain a different capability of the protection circuit for non-connection pins with respect to connection pins. The time constant of the protection circuit for the non-connection pins is made longer than that of the protection circuit for the connection pins. Further, the clamping capability for the connection pins is made greater than that for another connection pin adjacent to the connection pin.