Semiconductor package and manufacturing method thereof

Abstract

The invention discloses a semiconductor package and a manufacturing method thereof. The semiconductor package comprises a chip, chip surface protecting layers, chip bonding pads, lead on chip (LOC) tapes, pins, conducting components and resins, wherein the chip surface protecting layers are formed on the chip and cover the areas except the areas in which the chip bonding pads are about to form; the chip bonding pads are formed in the areas, which are not covered by the chip surface protecting layers, on the chip; the LOC tapes are formed on the chip surface protecting layers; the pins are formed on the LOC tapes which bond the pins and the chip surface protecting layers; the conducting components are formed on the chip bonding pads and part of the chip surface protecting layers and connect the chip bonding pads with the pins electrically; and the resins are used for packaging the components.

Description

technical field [0001] The invention relates to a semiconductor package and a manufacturing method thereof. More particularly, the present invention relates to a semiconductor package using conductive elements to interconnect chip pads with leads of a lead frame and a method of manufacturing the same. Background technique [0002] With the development of semiconductor packaging technology, higher requirements are put forward for the reliability and heat dissipation of the semiconductor package. figure 1 A schematic diagram of a lead on chip (LOC) package according to the prior art is shown. figure 2 shows that according to the prior art figure 1 A cross-sectional view of the LOC package shown in . [0003] refer to figure 1 and figure 2 , the semiconductor package 100 according to the prior art includes: a chip 10; a chip surface protection layer 14, formed above the chip 10, covering the area of ​​the chip 10 except the area where the chip pad 12 will be formed; the ...

AI Technical Summary

Problems solved by technology

[0004] The traditional LOC package uses the gold wire bonding method to interconnect the chip with the pins of the lead frame, which has the following disadvantages: the cost of the gold wire material and the equipment used is high; there are limitations to the interconnection of high-frequency chips ; The thermal performance of this LOC package is poor

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