Packaged semiconductor grain

Abstract

A semiconductor die featuring vertical rows of bonding pad structures is disclosed. The rows of bonding pad structures are located vertically in the Y direction, or traversing the width of the semiconductor die. A vertical row of bonding pad structures is located on each side of the semiconductor die while a third vertical row of bonding pad structures is located in the center of the semiconductor die. A first set of wire bonds connect each bonding pad structure located on the sides of the semiconductor die to a conductive lead structure located on a ceramic package. A second set of wire bonds connect each bonding pad structure located in the center of the semiconductor die to a lead on chip (LOC) structure located on the semiconductor die. The configuration of only vertical rows of bonding pad structures allows optimized parallel testing of the completed semiconductor chip to be accomplished when compared to testing performed on a semiconductor chip featuring both vertical and horizontal rows of bonding pad structures located on all sides of the semiconductor chip.

Description

technical field [0001] The invention relates to a method for manufacturing and testing a semiconductor chip, in particular to a pad design for a semiconductor chip or crystal grain, thereby realizing the best test of the semiconductor chip or crystal grain. Background technique [0002] The semiconductor industry continues to increase the performance of semiconductor chips while reducing the cost of manufacturing or processing those chips. Manufacturing cost reductions have been achieved by eliminating or integrating specific process steps or stages, such as directly depositing a doped semiconductor layer instead of the more time-consuming process of depositing a pure semiconductor material layer followed by doping. complex two-stage procedure. In addition, the development of advanced semiconductor equipment such as rapid thermal processing (rapid thermal processing (RTP)) also reduces the time required for a specific process. On the other hand, however, testing of the ent...

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Problems solved by technology

In prior art U.S. Patent Nos. US6,326,801 (Littlebury), US5,012,187 (Yasuda et al.), US6,469,327 (Loughmiller et al.), US6,396,300, and US4,685,998 (Quinn et al.), all disclose Various contact pad designs have been proposed, but the new pad design contained in the present invention has not been mentioned in the above-mentioned arts, especially the design of chip pads for improving testing and reducing costs has not been mentioned.

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