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Store to load forwarding predictor with untraining

A predictor, storage memory technology

Inactive Publication Date: 2005-07-06
ADVANCED MICRO DEVICES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Unfortunately, this can degrade performance if the load is executed incorrectly out of sequence and then subsequent corrective action is taken to get it right

Method used

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  • Store to load forwarding predictor with untraining
  • Store to load forwarding predictor with untraining
  • Store to load forwarding predictor with untraining

Examples

Experimental program
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Embodiment Construction

[0026] Processor Summary

[0027] see now figure 1 , a block diagram of an embodiment of a processor 10 is shown in the figure. Other embodiments are also possible and contemplated. exist figure 1 In the illustrated embodiment, processor 10 includes an instruction line predictor 12, an instruction cache (I-cache) 14, an alignment unit 16, a branch prediction / fetch PC generation unit 18, a plurality of decode units 24A-24D, a predictor miss decoding unit 26, a microcode unit 28, a mapping unit 30, a retirement queue 32, an architecture rename file 34, a future file 20, a scheduler 36, an integer Register file 38A, a floating point register file 38B, an integer execution core 40A, a floating point execution core 40B, a load / store unit 42, a data cache (D cache) 44, an external interface unit 46, and a PC storage area 48 . Instruction line predictor 12 is coupled to predictor miss decode unit 26 , branch prediction / fetch PC generation unit 18 , PC store 48 , and alignmen...

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Abstract

A processor 10 employs a store-to-load forwarding (STLF) predictor 60 that can indicate a dependency of dispatched load operations on a store operation. The dependency is indicated for a store operation that interfered with the execution of the load operation during a previous execution. Because dependencies related to the store are indicated, the load is not scheduled to precede the store and / or the load is not executed prior to the store. In response to executing a particular load and store and detecting the disturbance, the STLF predictor 60 is trained with information about the particular load and store. Furthermore, if the STLF predictor 60 indicates that a load operation is dependent on a particular store operation, and the dependency does not actually occur, the STLF predictor 60 may not be trained (e.g., the load operation associated with a particular load operation may be deleted). and information about stored jobs).

Description

Background of the invention [0001] technical field [0002] The present invention relates to processors, and more particularly to store-to-load forwarding mechanisms within processors. [0003] Background technique [0004] Processors often contain store queues to buffer memory jobs that have already been executed but are still in a speculative state. The store memory jobs may be held in a store queue until the memory jobs are retired. After retirement, the storage memory operations may be committed to cache and / or memory. In the usage herein, an in-memory job is a job that specifies a data transfer between a memory and a main memory (although the data transfer can also be done in a cache). A load memory job specifies the transfer of data from memory to the processor, and a store memory job specifies the transfer of data from the processor to memory. The memory operation may be an implicit part of an instruction that includes a memory operation, or it may be an explici...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38
CPCG06F9/3834G06F9/3826G06F9/3838G06F9/54G06F9/3856
Inventor J·B·凯勒T·S·格林W-H·利恩R·W·哈达德
Owner ADVANCED MICRO DEVICES INC
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