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Configuration and method for plannable control instruction and data access

A technology for data access and planning control, applied in the structural field of instruction and data access, which can solve problems such as waste of resources

Inactive Publication Date: 2005-11-02
SUNPLUS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, because the length of the cache data is fixed, it is still necessary to access the data with the length of the cache data, so unnecessary data will be read and stored, resulting in a waste of resources

Method used

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  • Configuration and method for plannable control instruction and data access
  • Configuration and method for plannable control instruction and data access
  • Configuration and method for plannable control instruction and data access

Examples

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Embodiment Construction

[0045] image 3 It shows the structure of the programmable control command and data access of the present invention. Between the first module 10 and the second module 20 in the computer system, a burst mode controller 33 is used to control the transmission of data. The first The module 10 can be a processor, a digital signal processor, a DMA master control device, a bus master, a specialized computing module, or other audio-visual processing modules, etc., and the second module 20 can be a memory, a DMA Slave device, bus slave device, HD / CD / DVD device, or network device, etc. In this embodiment, the first module 20 is a processor structure, which includes a processor core 31 and a fast access device 32, and the second module 20 is an external memory device 34, such as DRAM memory. The fast access device 32 stores part of the data from the external memory device 34, and provides a storage space for the processor core 31 to access data quickly, and the fast access device 32 ca...

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PUM

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Abstract

Multiple grades for transmitting data are preset in advance. Instructions and data in an external storage device are accessed in a present grade. Each grade of data transmission is relevant to an external storage device and a continuous length for transmitting data on interface of quick access device. Based on format of data accessed by the kernel of processor or result of decoding instructions by the kernel of processor, the present grade for transmitting data is adjusted.

Description

technical field [0001] The present invention relates to a structure and method for command and data access, especially a structure and method for planning control command and data access. Background technique [0002] In the structure of the processor of today's computer system, since the processing speed of the core of the processor is greatly increased, the memory access becomes the performance bottleneck. Therefore, the cache (Cache) structure becomes an important improvement method. Cache is to access the memory with the length of several fixed-length instructions or several data as a unit, and this unit is called a cache cluster (CacheLine). The size of the cache cluster is related to the access unit of the memory. For example, in many memories with the capability of burst transfer (Burst Transfer) nowadays, the data access can only be performed once after the address and various related settings are given, and then the specified burst length ( Burst Length) data stri...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/06G06F13/38
Inventor 梁伯嵩
Owner SUNPLUS TECH CO LTD