19 results about "Surface barrier" patented technology

A transistor device ac includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer, a source contact and a drain contact on the barrier layer, and a gate contact on the barrier layer between source contact and the drain contact. The device further includes a plurality of selective modified access regions at an upper surface of the barrier layer opposite the channel layer. The selective modified access regions include a material having a lower surface barrier height than the barrier layer, and the plurality of selective modified access regions are spaced apart on the barrier layer along a length of the gate contact.

The invention provides a semiconductor epitaxial structure and a preparation method and application thereof. A p-type semiconductor layer in the semiconductor epitaxial structure comprises a p-type barrier layer, the p-type barrier layer comprises at least one p-type structure, the p-type structure comprises a barrier front sub-layer, a p-type nitride microstructure and a barrier rear sub-layer which are arranged in sequence, and the p-type nitride microstructure comprises a plurality of nanometer protruding parts which are distributed on the surface, away from an active layer, of the barrier front sub-layer. The rear barrier sub-layer covers the plurality of nano convex parts and the surface, which is not covered by the nano convex parts, of the front barrier sub-layer; the material of the barrier front sub-layer is a first nitride doped with acceptor impurities, the material of the nanometer protruding part is a second nitride, and the valence band of the second nitride is higher than that of the first nitride. According to the invention, the p-type nitride microstructure is arranged in the p-type barrier layer so as to reduce the activation energy of acceptor doping, and a relatively strong polarization effect is formed at an interface, thereby cooperatively improving the hole concentration.

The invention relates to a ferroelectric memristor array and a sequential sequence processing method adopting the ferroelectric memristor array, and the ferroelectric memristor array comprises a bottom array gating structure which is used for providing unit-by-unit addressing and suppressing an undercurrent path of a non-gated unit in the array when the array scale is expanded; the adjustable conductive channel structure is used for generating a continuous photoconductive effect which can be accumulated and attenuated along with time under optical excitation; the in-plane polarization regulation and control structure modifies the conductive degree of the semiconductor channel by regulating and controlling the surface potential barrier of the channel so as to form a non-volatile weight state; and the multi-physical-quantity coupled electrode structure is used as a unified channel for weight regulation and control, conductivity reading and photoelectric response. Compared with the prior art, the semiconductor channel potential barrier is dynamically regulated and controlled through in-plane polarization of the ferroelectric film, non-volatile multi-stage conductance weight is achieved, synaptic-like photoresponse and short-time memory characteristics are obtained through the continuous photoconduction effect of a semiconductor material, and the continuous light input natural accumulation and attenuation process is achieved.

The invention discloses a composite barrier epitaxial material structure of an indium phosphide high-mobility transistor and a buried gate control method of the composite barrier epitaxial material structure. The device sequentially comprises a semi-insulating indium phosphide substrate, a buffer layer, a channel layer, an isolation layer, a doping layer, an inner barrier layer, a buried gate stop layer, a surface barrier layer, an InP corrosion self-stop layer and a cap layer from bottom to top. The buried gate control method comprises the following steps: firstly, preparing a 4-inch InP wafer, and simultaneously completing isolation and source-drain ohmic contact pre-process; an InP HEMT grid electrode is prepared; performing buried gate process heat treatment; other front and back processes are completed, and independent chips are formed through cutting-up. According to the invention, an InP-InAlAs-InGaP composite barrier structure is provided in an epitaxial structure, stable diffusion Schottky contact is formed by adopting a buried gate process, and an InGaP buried gate stop layer is added, so that the buried gate depth is controllable. The InP HEMT device has the characteristics of low noise, low power consumption, high breakdown voltage and the like, and can meet the use requirements of an InP HEMT low-noise amplifier in application scenes of quantum bit reading, radio astronomy, remote sensing imaging and the like.

An ultrasonic automatic flaw detection device belongs to the technical field of ultrasonic flaw detection, and aims to solve the problems that surface interference is mistakenly judged as internal cracks or inclusions and damage is caused by direct contact between a probe and a large shaft. The ultrasonic automatic flaw detection device comprises a rack, a driving part is mounted in the rack, and a moving plate is arranged on the surface of the driving part; a high-frequency alternating magnetic field is excited through the electromagnetic coil, obstacles such as rust layer protrusions and weld beading on the surface of the large shaft can be penetrated, ultrasonic waves are directly generated in a metal base body, an ultrasonic probe does not need to make contact with the large shaft, on one hand, the ultrasonic probe is not prone to damage, and on the other hand, the ultrasonic probe is not prone to damage. On the one hand, false signals generated by barrier reflection of a traditional contact type probe are avoided, the misjudgment rate is reduced, on the other hand, ultrasonic reflected waves can be received through air coupling without a coupling agent, energy loss caused by non-uniform smearing of the coupling agent is reduced, and interference of surface barriers on detection is eliminated.

The application provides a coating material system with synergistic effect of a barrier layer and an oxidation-resistant layer on a metal surface, which is composed of a first protective layer formed by Y2O3 and / or CeO2 and a second protective layer formed by Ni-55Al-12Si-Y-Hf-Zr. The application fully utilizes the synergistic effect between the first protective layer formed by Y2O3 and / or CeO2 and the second protective layer formed by Ni-55Al-12Si-Y-Hf-Zr, so that the coating material system can realize long-term oxidation resistance of a hot end part of a gas turbine at 1000-1100 DEG C. The application also provides a preparation method of the coating material system with synergistic effect of a barrier layer and an oxidation-resistant layer on a metal surface. The method uses a supersaturated solution immersion method to prepare the first protective layer composed of Y2O3 and / or CeO2, and further uses a slurry method to prepare the second protective layer composed of Ni-55Al-12Si-Y-Hf-Zr on the basis of the first protective layer, so that the coating material system is uniform and dense, and the uniformity of the coating material system can be ensured even for a hot end part with a complex inner cavity and an outer shape structure at a small angle.

The invention discloses a tellurium-cadmium-mercury unipolar barrier structure with an epitaxial layer stress constraint function and a preparation method, and relates to an infrared focal plane technology. The prestress layer is deposited on the surface of the substrate and used for providing initial stress constraint in the epitaxial process; the strain buffer layer is located between the prestress layer and the absorption layer, is of a symmetrical superlattice structure and is used for limiting stress in a plane in the epitaxial process to achieve coherent growth of atoms; the absorption layer is epitaxially arranged on the surface of the strain buffer layer; the barrier layer is epitaxially arranged on the surface of the absorption layer, and the structure of the barrier layer is a nested superlattice structure formed by superlattices and CdZnTe layers alternately; and the cover layer extends on the surface of the barrier layer. The high-efficiency barrier barrier layer structure with aligned valence bands can be ensured, so that the epitaxial crystal quality is improved, the dark current performance is improved, and the epitaxial process and the structural internal stress relaxation effect of the unipolar barrier type detector structure are improved.

The invention discloses a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors, and the semiconductor device comprises an insulating layer, a channel layer and a barrier layer. The channel layer is located on the first surface of the insulating layer; the barrier layer is located on the surface of one side of the channel layer away from the insulating layer; a source electrode, a grid electrode and a drain electrode are sequentially arranged on the surface of one side, far away from the channel layer, of the barrier layer; the grid electrode, the source electrode and the drain electrode are arranged at intervals; a region between the grid electrode and the drain electrode comprises a first region and a second region surrounding the first region, an isolation structure is arranged between the first region and the second region, and the isolation structure extends to the insulating layer from the surface of one side, far away from the channel layer, of the barrier layer; the first region includes a diode structure in thermal contact with the channel layer for detecting a temperature of the channel layer. The diode structure in thermal contact with the channel layer is arranged in the first region of the semiconductor device, and the isolation structure is arranged between the first region and the second region, so that the accuracy of monitoring the junction temperature of the semiconductor device is improved.

The invention relates to the technical field of pBn detectors, in particular to an InAs / InAsSb superlattice medium-wave infrared pBn detector structure and a preparation method thereof, and the InAs / InAsSb superlattice medium-wave infrared pBn detector structure comprises a GaSb substrate, a GaSb buffer layer, a p < + >-GaSb contact layer, an InAs / InAsSb superlattice absorption layer, an AlAs < 0.08 > Sb < 0.92 > barrier layer, an n < + >-InAsSb contact layer, an InAs cover layer, a metal electrode I and a metal electrode II. The InAs / InAsSb superlattice absorption layer is arranged on the upper surface of the p < + >-GaSb contact layer, and the AlAs < 0.08 > Sb < 0.92 > barrier layer is arranged on the upper surface of the InAs / InAsSb superlattice absorption layer; according to the InAs / InAsSb superlattice medium-wave infrared pBn detector structure, band gap regulation and control, low dark current and good electrical contact performance can be considered at the same time.

Embodiments described herein include a vessel, for example, a beverage container, configured for containing a liquid. The vessel may be formed of a metal body and includes an interior surface barrier layer with a pre-determined surface roughness. In embodiments, the interior surface barrier layer includes a mirror-like, highly reflective finish. In additional or alternative embodiments, the interior surface barrier layer includes an oxide of chromium. In embodiments, the interior surface barrier layer substantially prevents chemical components from the metal body from leaching into the contained liquid. In embodiments, the interior surface barrier layer promotes cleanability and / or sterilization for vessel reuse.

The utility model relates to a foot side sensing device, a shoe pad, a shoe, a sock and a machine sole fixture. The foot side sensing device comprises a CDC, a switch array, a digital processing circuit and a side sensing unit laid on the side of a foot. Each group of side surface sensing units comprises at least two flexible outer electrodes, the outer electrodes form mutual capacitance and / or self-capacitance for detecting approaching of a side surface obstacle, a bulge is formed on the inward side of each outer electrode, the outer surface of each bulge is an elastic curved surface, an inner electrode is arranged in the inward direction of each bulge, an inner insulating layer is arranged between each bulge and the corresponding inner electrode, and the outer surface of each bulge is an elastic curved surface. The outer electrode is deformed by an external force to change the indirect contact area of the involved bulge on each corresponding inner electrode; the CDC is respectively coupled with each inner electrode and is respectively coupled with each outer electrode through the switch array, and the switch array is used as the outer electrode and is coupled to a time-sharing gating channel of the CDC or the ground; and the digital processing circuit is used for logic processing and / or logic sequence control and is respectively coupled with the CDC and the switch array.

The invention belongs to the technical field of batteries, and provides a composite metal lithium negative electrode, a preparation method thereof and a battery, the composite metal lithium negative electrode comprises a metal lithium base layer, and a first passivation layer, an intermediate polymer layer and a surface barrier layer are sequentially arranged in the thickness direction of the metal lithium base layer; the first passivation layer comprises lithium sulfide and an organic sulfur derivative; the middle polymer layer comprises a first polymer matrix, a lithium salt and a functional additive; the surface barrier layer comprises a second polymer matrix and an inorganic solid electrolyte. By arranging the first passivation layer, the middle polymer layer and the surface barrier layer on the metal lithium base layer, a gradient functionalized multi-layer synergistic protection structure is formed, a closed loop mechanism of chemical passivation-ion regulation-physical barrier is realized, and the problems of SEI film stability, lithium ion uniform transmission and dendritic crystal growth are solved.

The invention provides a method for predicting secondary electron emission time based on Monte Carlo, and the method comprises the following steps: 1, obtaining the fluctuation height and the maximum fluctuation height; 2, determining incident electron characteristics and material types, and setting an initial moment; step 3, simulating an electron scattering and internal secondary electron generation process and calculating a scattering step length; 4, judging whether scattering is in the material or not, if yes, calculating and updating the moment to the step 3, and otherwise, executing the step 5; 5, judging whether the surface potential barrier is traversed or not, and if not, returning to the updating moment to the step 3; otherwise, updating the time to step 6; step 6, judging whether re-incidence occurs or not, if no, updating the moment, and obtaining the secondary electron emission moment; otherwise, calculating the time to the re-incidence point and updating the time, and going to the step 3; and step 7, counting all electron moments to obtain secondary electron emission time. According to the method disclosed by the invention, all durations of electrons from entering the material to generating secondary electrons and completely emitting from the surface are obtained, and the secondary electron emission time characteristic is obtained.

A light emitting module unit includes a circuit board and a light emitting device. The light emitting device includes a plurality of light emitting elements electrically coupled through the circuit board, one or more electrodes arranged on a first surface of the plurality of light emitting elements, a surface barrier formed on a second surface of one or more of the plurality of light emitting elements, and an encapsulation portion disposed above a third surface of the plurality of light emitting elements. The surface barrier is disposed between the encapsulation portion and the second surface of one or more of the plurality of light emitting elements.

The subject of the application, shown in the drawing, is a device and method for cooling photovoltaic panels with an airflow generated by a surface barrier discharge to improve their efficiency under elevated temperatures. The device's design enables the generation of an airflow to cool the underside of the photovoltaic panel. A surface barrier discharge battery, which has no moving parts and is weather-resistant, is used to generate the airflow.

The application relates to the technical field of electronic component manufacturing, and discloses a special integrated cap for aluminum shell resistors and a production process thereof, which comprises a bare integrated cap and a pure tin plating layer covering the surface of the cap. The plating layer is made by step-by-step plating of A-slot high-temperature fixed-planting liquid and B-slot low-temperature pulse liquid. The production process is as follows: low-carbon steel wires are continuously punched to form the bare integrated cap and pretreated; the cap is immersed in the A-slot high-temperature fixed-planting liquid to perform cathode direct-current barrel plating, so that the accelerator is pre-adsorbed in the deep hole; the liquid in the tank is taken out and exposed in the air to establish a chemical gradient of passivation outside the hole and activity inside the hole; then the cap is immersed in the B-slot low-temperature pulse liquid to perform barrel plating by using an outer surface barrier layer formed by branched polyethylene imine and an asymmetric reverse pulse power source; and finally, the cap is washed with water and dried by hot air centrifugal drying. The application cooperates a double-tank heterogeneous system with pulse plating to eliminate the contact resistance of split splicing, improve the plating leakage condition of deep holes and blind hole parts of the cap body, and improve the uniformity and firmness of the plating layer of the product.

The application provides a kind of high barrier PET blister tray composite material and preparation method thereof, it is related to PET blister tray technical field, including the base PET layer, gradient barrier intermediate layer and surface barrier coating layer that are sequentially stacked from inside to outside by composite.The application effectively overcomes the industry pain points of traditional PET / EVOH multilayer material interlayer easy peeling, EVOH hydrophilic barrier loss and heat forming size instability, the gradient intermediate layer uses in-situ reaction blending and nanosheet intercalation to construct long-range tortuous diffusion path, cooperates with atmospheric pressure plasma treatment to generate high-density-COOH / -OH active sites in-situ at interface, makes ultra-thin SiO2-GPTMS hybrid coating and base film form covalent bond level chemical anchoring, maintains ≥88% light transmittance, ≤0.8% heat shrinkage and 85℃ / 85%RH aging 500h after ≤5% barrier attenuation rate of long-term stability under 110℃ blister heat forming conditions, provides ideal packaging solution for food, medicine and precision electronics and other high-sensitivity products, which has extreme freshness and moisture-proof, excellent heat processing adaptability and full life cycle reliability.

The application provides a semiconductor epitaxial structure, a preparation method and application thereof. The p-type semiconductor layer of the semiconductor epitaxial structure comprises a p-type barrier layer, the p-type barrier layer comprises at least one p-type structure, the p-type structure comprises a barrier front sublayer, a p-type nitride microstructure and a barrier rear sublayer arranged in sequence, the p-type nitride microstructure comprises a plurality of nano protrusions distributed on the surface of the barrier front sublayer away from the active layer, the barrier rear sublayer covers the plurality of nano protrusions and the surface of the barrier front sublayer not covered by the nano protrusions; the material of the barrier front sublayer is a first nitride doped with an acceptor impurity, the material of the nano protrusions is a second nitride, and the valence band of the second nitride is higher than that of the first nitride. The p-type nitride microstructure is arranged in the p-type barrier layer to reduce the activation energy of the acceptor doping, and a stronger polarization effect is formed at the interface, so that the hole concentration is improved.

This invention belongs to the field of heat pipe technology, specifically relating to a method for controlling and online evaluating the content of non-condensable gases in high-temperature heat pipes. The invention includes the following steps: S1, deep cleaning of materials to eliminate non-condensable gases and other impurities dissolved or adsorbed from the end caps, shell, wick, and filling tube; S2, process cleaning to ensure that no new contaminants are introduced during assembly and welding; S3, heat pipe purification and venting to complete the injection of the working fluid and the final purification and venting within the heat pipe; S4, long-term surface barrier to prevent helium and hydrogen from permeating into the heat pipe. This invention addresses the entire process from materials, manufacturing, filling, and testing, achieving proactive and precise control and quantitative evaluation of non-condensable gas content from three dimensions: source control, process elimination, and online evaluation. This improves the long-term reliability and performance consistency of heat pipes under various complex environments.