Camera device
By sharing the drive circuit and signal processing circuit, time-division image signal processing of multiple solid-state imaging elements is realized, which solves the problems of large circuit scale and high power consumption in the existing technology, and improves the operation efficiency and image quality of the imaging device.
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Embodiment 1
[0032] FIG. 3 is a block diagram showing a schematic configuration of the imaging device 100 according to Embodiment 1 of the present invention. The imaging device 100 has the first and the second CCD solid-state imaging elements (hereinafter referred to as CCD) 31a, 31b, the first and the second voltage boosting circuits 32a, 32b, the first and the second CCD drive circuits 33a, 33b, the timing control circuit 34, the first 1 and 2 clamping circuits 35a, 35b, selection circuit 36, analog signal processing circuit 37, A / D conversion circuit 38 and digital signal processing circuit 39.
[0033] The first CCD 31a is, for example, a frame transfer type solid-state imaging device as shown in FIG. 4 . The first CCD 31a includes a plurality of vertical shift registers 1v connecting the imaging unit to the storage unit, a horizontal shift register 1h disposed on the output side of the plurality of vertical shift registers 1v, and an output unit 1d disposed on the output side of the h...
Embodiment 2
[0075] FIG. 10 is a block diagram showing a schematic configuration of an imaging device 200 according to Embodiment 2 of the present invention. In the second embodiment, the difference from the first embodiment is that a common booster circuit 51 and clamp circuit 35 are further configured.
[0076] The boost circuit 51 includes a boost unit 51a and an output selection unit 51b. The booster 51a generates a boosted voltage by boosting the supplied power supply voltage Vd (not shown), and the output selection unit 51b switches the supply destination of the boosted voltage according to the operation time of the first CCD31a and the second CCD31b.
[0077] The boost circuit 51 supplies the boosted voltage to the first CCD 31a and the first CCD drive circuit 33a when driving the first CCD 31a, and supplies the boosted voltage to the second CCD 31b and the second CCD drive circuit 33b when driving the second CCD 31b. The switching of the output selection unit 51 b is controlled by...
Embodiment 3
[0084] FIG. 11 is a block diagram showing a schematic configuration of an imaging device 300 according to Embodiment 3 of the present invention. In the third embodiment, the difference from the first embodiment is that independent timing control circuits are respectively provided for the first and second CCDs 31a and 31b.
[0085] The first and second timing control circuits 50a, 50b are respectively provided corresponding to the first and second CCDs 31a, 31b, and each independently operates. The first and second timing control circuits 50a and 50b have the same configuration, and include a counter for counting the reference clock signal CK of a certain period and a decoder for decoding the output of the counter. The first and second timing control circuits 50a and 50b can generate a plurality of timing signals of different formats by changing the setting values of the decoders.
[0086] In the imaging device 300, for example, when the first CCD 31a is driven, a timing sig...
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