Digital interface circuit in light synchronous digit transmission system and its data demultiplexing method
An optical synchronization digital and digital interface technology, applied in transmission systems, electromagnetic wave transmission systems, multiplexing communications, etc. methods, etc., to increase the degree of adaptation and flexibility, weaken the impact of data recovery, and increase stability and fault tolerance.
Active Publication Date: 2007-07-25
SANECHIPS TECH CO LTD
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However, this multiplexing and demultiplexing interface only gives the input signal and the timing characteristics of the interface, and does not give the internal specific structure and the method of demultiplexing data demarcation, so how to implement it is unknown to those skilled in the art.
Moreover, the multiplexing and demultiplexing TELECOMBUS interface is only output in a sequential relationship, which undoubtedly increases the difficulty of system design and debugging.
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[0035] Below in conjunction with accompanying drawing, the present invention is described in further detail:
[0036]A digital interface circuit in an optical synchronous digital transmission system of the present invention includes a data multiplexing module, as shown in Figure 3, the data multiplexing module multiplexes 8-bit data into 2-bit data, and The 4 indication signals are multiplexed into 1 status indication signal, which can select the corresponding timing of sending data and clock, and send the alarm information configured by the CPU interface. It includes a clock edge generation submodule 10 , a sending timing counting submodule 11 , a sending timing selection submodule 12 , an alarm and timing configuration submodule 14 and a data multiplexing submodule 13 .
[0037] The clock edge generating sub-module 10 uses the fast clock to sample the slow clock in the multiplexed asynchronous clock domain, and then obtains the corresponding relationship between the fast clo...
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The invention relates to a digital interface circuit and the data demux method in optical synchronous digital transmission system. The interface circuit includes a data multiplexing model and a data demultiplexing. The data multiplexing model multiplexes the data, data with preset quantity are multiplexed into a state instructing signal, selects the correspondent time sequence of transmitting data and clock, sends out the warning information of interface configuration of the CPU, it also includes a clock edge generating sub-model, transmitting sequence counting sub-model, transmitting sequence selecting sub-model, warning and sequence configuration sub-model, data multiplexing sub-model. The invention designs the data definition sub-model, creates a data definition state machine, and provides a demultiplexing method for interface data, it increases the stability and tolerant of data restoration, weakens the affection to data restoration by the level fluctuation of the system.
Description
technical field [0001] The present invention relates to the field of optical synchronous digital transmission (abbreviated as SDH / SONET), in particular to a digital interface circuit between data from the access layer to the switching layer in the optical synchronous digital transmission system. Background technique [0002] The optical synchronous digital transmission system is generally composed of two basic equipments: transmission equipment and network nodes. For the optical synchronous digital transmission system, the transmission equipment is the optical cable system, and the network nodes are more complex, including termination equipment (TM), cross-connection equipment (DXC), Multiplexing Device (ADM), etc. The most basic and important module signal in the optical synchronous digital transmission system is the STM-1 signal with a line rate of 155.520Mbit / s. The STM-N signal is the synchronous multiplexing of the basic module signal STM-1 and interleaved bytes As a r...
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IPC IPC(8): H04B10/02H04L29/10H04J3/06
Inventor 田小峰
Owner SANECHIPS TECH CO LTD