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Method for producing ferroelectric memory cells

A ferroelectric and memory technology, used in electrical components, semiconductor/solid-state device manufacturing, circuits, etc.

Inactive Publication Date: 2007-08-08
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, during the annealing step of the ferroelectric, the oxidation of the oxygen diffusion barrier, and in particular the bonding layer below it, and the polysilicon or tungsten plug or its sides is unavoidable

Method used

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  • Method for producing ferroelectric memory cells
  • Method for producing ferroelectric memory cells
  • Method for producing ferroelectric memory cells

Examples

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Embodiment Construction

[0038] 1, 2A and 2B have been described in detail above, and FIG. 3 (similar to FIG. 1) shows a partial cross-sectional view of a ferroelectric memory cell fabricated according to the principle of stacked cells, and shows important variables of the method according to the invention. These variables include: d BARR , which represents the layer thickness of the layer system comprising the tie layer 2,3 and the oxygen diffusion barrier 4,5; b BARR , which represents half the layer width of the layer system comprising the tie layer 2,3 and the oxygen diffusion barrier 4,5; D oxygen (thick arrow), which represents the oxygen diffusion coefficient (temperature dependent) of the material of the bonding layer 2, 3; D silicon (lower thick arrow), which represents the silicon diffusion coefficient (temperature-dependent) of the material of the bonding layer 2,3, which determines the silicidation reaction of the bonding layer 2,3.

[0039] [(d BARR ) 2 / D silicon ]BARR ) 2 / D oxyg...

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Abstract

The invention relates to a method for producing ferroelectric memory cells in accordance with the stack principle. According to said method, an adhesive layer (2, 3) is formed between a lower capacitor electrode (6) of a memory capacitor and a conductive plug (1), which is formed below said electrode and makes an electric connection between said capacitor electrode (6) and a transistor electrode of a selection transistor that is formed in or on a semiconductor wafer. An oxygen diffusion barrier (4, 5) is formed above the adhesive layer and once the ferroelectric has been deposited, the adhesive layer and the barrier are subjected to rapid thermal processing (RTP) in an oxygen atmosphere. The method is characterised by the following steps: (A) Determination of the oxygen speed of the adhesive layer (2, 3) and the diffusion coefficient (DOxygen(T)) of oxygen in the material of the adhesive layer (2, 3), dependent on the temperature (T); (B) Determination of the diffusion coefficient (DSilicon(T)) of silicon in the material of the adhesive layer (2, 3), dependent on the temperature and (C) Calculation of an optimal temperature range for the RTP step from the two diffusion coefficients, (DOxygen(T)) and (DSilicon(T)) that have been determined for a predetermined layer thickness (dBARR) and layer width (bBARR) of the layer system consisting of the adhesive layer and the oxygen diffusion barrier, so that during the RTP step the siliconisation of the adhesive layer occurs more rapidly than its oxidation.

Description

technical field [0001] The present invention relates to a method of manufacturing ferroelectric memory cells based on the principle of stacking, wherein a bonding layer is formed between the lower capacitor electrode of a storage capacitor and a conductive polysilicon plug below the storage capacitor to electrically connect the lower capacitor electrode Transistor electrodes connected to selection transistors, wherein the selection transistors are formed inside or on the surface of the semiconductor wafer, and an oxygen diffusion layer is formed over the junction layer, and after deposition of the ferroelectric substance, rapid thermal processing (RTP ). Background technique [0002] In the case of ferroelectric memory cells fabricated according to the stacking principle, transistors are usually fabricated inside or on the surface of a semiconductor wafer. Subsequently, an intermediate oxide layer is deposited over the entire semiconductor wafer. Ferroelectric capacitor mo...

Claims

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Application Information

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IPC IPC(8): H01L21/8246H01L21/02H01L21/768H01L27/105
CPCH01L21/76855H01L21/76888H01L21/7687H01L28/75H01L28/55H01L27/105
Inventor I·卡斯科M·克罗恩科
Owner INFINEON TECH AG
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