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Semiconductor device and producing method thereof

A device manufacturing method and manufacturing method technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., capable of solving problems such as short circuits in memory cell regions

Inactive Publication Date: 2003-06-11
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when performing silicidation by covering the entire underlayer with metal silicide at the time of dry etching, there is a problem that a short circuit is generated between bit lines in the memory cell region.

Method used

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  • Semiconductor device and producing method thereof
  • Semiconductor device and producing method thereof
  • Semiconductor device and producing method thereof

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example -

[0082] In this embodiment, a so-called embedded bit line type flash memory (SONOS type flash memory) is shown as an example of a semiconductor device. The structure of the flash memory is described here in combination with its manufacturing method for convenience.

[0083] Figure 1 to Figure 6 Plan view for showing the manufacturing method of the SONOS type flash memory according to the first embodiment in the order of processes, and Figure 7A with Figure 7B Its schematic cross-sectional view.

[0084] To manufacture this flash memory, as figure 1 As shown in , first prepare a p-type silicon semiconductor substrate 1 . On the surface of the semiconductor substrate 1, thermal oxidation is performed at a temperature of 900°C to 1000°C by, for example, a LOCOS (Local Oxidation of Silicon) method, and a film of about 200 nm to about 500 nm in thickness is formed in the element isolation region. Field oxide film (field oxide film) 2. Thereby, element isolation is performe...

no. 2 example -

[0119] Next, a second embodiment of the present invention will be described. The manufacturing method of the SONOS type flash memory in the second embodiment is basically the same as that of the first embodiment. However, the difference is that the shape of the protective film is different when the bit line is silicided. Note that the same reference numerals and symbols are used to designate the same components and the like as those of the first embodiment, and thus descriptions thereof will be omitted.

[0120] Figure 12 with Figure 13 14 is a plan view showing main processes of a manufacturing method of a SONOS type flash memory according to the second embodiment, and FIG. 14 is a sectional view showing the SONOS type flash memory.

[0121] In a similar manner to the first embodiment above Figure 1 to Figure 3 After each of the treatments, a silicon oxide film is first deposited on the entire surface by the CVD method. Then, if Figure 12 As shown in , on this silic...

no. 3 example -

[0137] Next, a third embodiment of the present invention will be described. The manufacturing method of the SONOS type flash memory in this third embodiment is basically the same as that in the first embodiment. However, the difference is that the shape of the protective film is different when the bit line is silicided. Note that the same reference numerals and symbols are used to designate the same components and the like as those of the first embodiment, and thus descriptions thereof will be omitted.

[0138] Figure 16 with Figure 17 is a plan view showing main processes of the manufacturing method of the SONOS type flash memory according to the third embodiment, and Figure 18A with Figure 18B is a cross-sectional view showing the SONOS type flash memory.

[0139] In a similar manner to the first embodiment above Figure 1 to Figure 3 After each of the treatments, a silicon oxide film is first deposited on the entire surface by the CVD method. Then, if Figure 16 A...

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Abstract

A resist pattern is formed on a silicon oxide film. This resist pattern is formed in such a shape to expose only portions necessary for electrical insulation between bit lines adjacent to each other. In other words, here, these portions are a connection hole forming region in which a contact hole of the bit line is formed and a connection hole forming region in which a contact hole of a word line is formed. Using this resist pattern as a mask, an insulation region is formed by full anisotropic etching of the silicon oxide film. Siliciding is performed in this state and silicide is formed on a surface of the bit line exposed to the connection hole forming region and a surface of a source / drain in an active region of a peripheral circuit.

Description

[0001] Cross References to Related Applications [0002] This application is based on and claims priority from Japanese Patent Application No. 2001-374840 filed on December 7, 2001, the contents of which are hereby incorporated by reference. technical field [0003] The present invention relates to a semiconductor device and a method of manufacturing the same, wherein a bit line is formed of an impurity diffusion layer, and a word line is formed to cross the bit line via an insulating film having a charge trap function or a floating gate. Background technique [0004] Generally, as a nonvolatile memory capable of retaining stored information even when the power is turned off, such a semiconductor memory has been developed in which an impurity diffusion layer formed on a semiconductor substrate forms a bit line (embedded bit line), And the word line is formed on the semiconductor substrate through the capacitor insulating film so as to form a right angle with the bit line. I...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8246H01L21/8247H01L27/10H01L27/115H01L29/788H01L29/792
CPCH01L27/11531H01L27/11526H01L27/11521H01L27/115H01L27/11568H10B41/42H10B41/40H10B69/00H10B41/30H10B43/30H01L27/10H10B99/00
Inventor 高桥浩司吉村铁夫
Owner FUJITSU LTD
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