Stack speed process method in Ethernet exchanger

Abstract

In the stack chain constituted by exchange chips, the normal forwarding flow of the data frames received by exchange chips passing through is as follows. (A) Data frames are received. (B) The protocol process of the frame and looking up the forwarding target port of the frame. (C) Determining whether the target port is the local port. If yes, the frame is sent to the target port through the flow (D). The characters are that before the flow (B), the stack process branch is setup to determine whether the source port is the stack port. At least for the data frame, whose source port is the stack port, the determination of whether the current chip is the end of the stack chain is carried out. If the current chip is not at the end of the stack chain, the data is sent to next stack port quickly.

Description

[technical field] [0001] The invention relates to electric communication technology, in particular to a method for processing speed-up by stacking of Ethernet switches. [Background technique] [0002] Such as Figure 1 to Figure 3 This is a schematic diagram of implementing multi-chip stacking using stacking links. "Rx / Tx" in the above figures indicates the "receiving / transmitting" direction of a certain Ethernet physical port. The simplex stacking mode means that only one port of a switching chip is connected to the stacking link, and the sending direction of the stacking port is connected to the receiving direction of the stacking port of the next switching chip, which are connected in turn to form a ring, such as figure 1 As shown, a feature of this stacking method is that there are no edge devices, and all switching chips are in the same relative position. [0003] The duplex stacking mode is that each chip has two ports connected to the stacking link, and the "receive...

AI Technical Summary

Problems solved by technology

[0014] Requires many software operations, complex design, poor performance

[0015] 2. All frames on the stack link must go through the entire link so that other chips can also learn

The disadvantage of this technology is: the forwarding process of each chip is basically fixed, and the delay is also fixed. For each data fram

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