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Patterning process of circuit base board

A patterned process and circuit substrate technology, applied in the direction of conductive pattern formation, circuits, electrical components, etc., can solve problems such as low production efficiency, waste of production costs, and inability to satisfy customers

Inactive Publication Date: 2003-12-03
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] 1. The production of circuit wiring lines in the prior art generally requires the use of exposure and development processes, not only the production cost is high, but also the production is extremely time-consuming and the production efficiency is too low
[0012] 2. It is difficult to manufacture high-quality through holes, the manufacturing process is extremely complicated, the production time is too long, and the cost of machine equipment is very expensive and the cost is too high
[0013] From the above description, it can be seen that the substrates of integrated circuits manufactured by the existing technology have disadvantages such as poor reliability and poor strength of conductive plug holes, and often fail to meet the standards required by customers, which not only affects the competitiveness of the market but also causes production. The cost is wasted, so manufacturers engaged in substrate production are all committed to improving the through-hole process to improve the reliability of the substrate and achieve the goal of increasing market competitiveness and reducing production costs

Method used

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  • Patterning process of circuit base board
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  • Patterning process of circuit base board

Examples

Experimental program
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Effect test

no. 1 example

[0026] Figure 2A to Figure 2N It is a schematic diagram of the patterning process of the circuit substrate of the first embodiment of the present invention, and its steps include:

[0027] (a) First provide a stamp 1 formed by a master mold, the stamp 1 is an elastic base material (elastomeric base), such as dimethylsilane polymer (poly dimethylsiloxane, referred to as PDMS), etc., the stamp 1 and has been patterned to form a number of patterns 1a, the pattern 1a is corresponding to the circuit wiring pattern of the circuit substrate to be made later; the stamp 1 is immersed in a self-assembly molecular solution 2, and the self-assembly molecular solution 2 such as OTS (ie Octadecyltrichlorosilane), RSiCl 3 , RSi(OCH 3 ) and other solutions, which have the property of inhibiting metal nucleation, such as Figure 2A shown.

[0028] (b) remove the stamp 1 from the self-assembled molecular solution 2, on which a film that inhibits metal nucleation properties has been adsorbe...

no. 2 example

[0042] Figure 3A to Figure 3G It is a schematic diagram of the patterning process of the circuit substrate of the second embodiment of the present invention. The technical points are the same as those of the first embodiment, but the detailed implementation steps are different. The steps include:

[0043] (a) First provide a circuit substrate 31, same as above-mentioned embodiment, this circuit substrate 31 can be as general unit circuit sheet, hard ceramic substrate or plastic substrate, soft substrate etc., also can be circuit board or core board etc., this circuit A number of through-holes 32 that penetrate the circuit substrate 31 and have been filled are formed at predetermined positions of the substrate 31; a dielectric layer 33 is covered on the surface of the circuit substrate 31, which is a photosensitive dielectric layer or a laser processable layer ,Such as Figure 3A shown.

[0044] (b) If the dielectric layer 33 is a photosensitive dielectric layer, then use st...

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Abstract

A patterning process for PCB is suitable to prepare very fine wires and very small holes on the PCB, and includes providing a print plate, attaching a film able to suppress metal nudeation to the surface of print plate, making the print plate in contact with the surface of PCB, transferring the film onto the PCB, transferring the film onto the PCB, and depositing metal layer on the area uncovered by self-assembling moleculae to form a patterned metal layer.

Description

technical field [0001] The invention relates to a patterning process of a circuit substrate, in particular to a film that has the property of inhibiting metal nucleation by adsorption, such as a stamp of a self-assembled monolayer film (Self-Assembled Monolayers, also known as a self-assembled molecular layer) (stamp), the process of performing selective deposition of metal layers on the circuit substrate to form tiny via holes and circuit patterns. Background technique [0002] At present, the multi-layer integrated circuit substrates manufactured by circuit board or substrate manufacturers tend to be miniaturized. Not only the line width of the circuit wiring is extremely thin, but also the through holes (via) and via holes of the circuit wiring conduction pipes are arranged. (Plate Through Hole, referred to as PTH), etc., the pore diameter is below 100 μm, and the line width is even below 50 μm. Therefore, in order to achieve higher density and precision requirements, th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/12H05K3/12
Inventor 宫振越何昆耀
Owner VIA TECH INC