Unlock instant, AI-driven research and patent intelligence for your innovation.

Clock generating circuit and generating method

A clock generation circuit and generation method technology, applied in the direction of electrical components, automatic power control, etc., can solve the problems of time and cost loss, and achieve the effect of saving time and cost loss

Inactive Publication Date: 2004-11-24
PROLIFIC TECH INC
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, no matter whether the method of phase-locked loop or digital state diagram is used to generate the required clock, the frequency ratio between it and the system clock is fixed after the design is completed, and when the system clock frequency or the required clock frequency changes, it will Can only redesign the circuit, resulting in loss of time and cost

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Clock generating circuit and generating method
  • Clock generating circuit and generating method
  • Clock generating circuit and generating method

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0031] Please refer to figure 1 As shown, it is a schematic diagram of a clock generation circuit according to the first embodiment of the present invention. As shown in the figure, the clock generating circuit 100 includes: a register 110 , a first adder 120 , a first comparator 130 , a second adder 140 and a multiplexer 150 . Of course, as shown in the figure, in order to adjust the duty of the generated output clock, the clock generating circuit 100 preferably further includes a second comparator 160 .

[0032] Wherein, assuming that the frequency of the system clock SYSCLK is 34 MHz, and the frequency of the first output clock CLK1 or the second output clock CLK2 to be generated is 10 MHz, the ratio of the frequency of the first output clock CLK1 to the system clock SYSCLK is 10M / 34M. In order to simplify the circuit, the greatest common divisor of the frequencies of the first output clock CLK1 and the system clock SYSCLK is first calculated, which is 2M in this example, ...

no. 2 example

[0044] Please refer to image 3 As shown, it is a schematic diagram of a clock generation circuit according to the second embodiment of the present invention. The difference between this embodiment and the first embodiment is that the first embodiment uses the method of progressive data value, but this embodiment adopts the approach of decreasing data value. As shown in the figure, the clock generating circuit 300 also includes: a register 310 , a first adder 320 , a first comparator 330 , a second adder 340 and a multiplexer 350 . Of course, as shown in the figure, in order to adjust the period ratio of the generated output clock, the clock generating circuit 300 preferably further includes a second comparator 360 .

[0045] It is also assumed here that the description of the system clock SYSCLK, the first output clock CLK1 and the second output clock CLK2 in the first embodiment is continued, that is, the values ​​of the first set value A and the second set value B are 5 an...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The present invention relates to a clock generation circuit and its generation method. It is characterized by that said method includes the following steps: calculating the frequency ratio valve of output clock and system clock in advance, said frequency ratio value is that first set value is divided by second set value, then using a buffering memory to store an information value and using first adder to obtain the sum of information value and first set value to produce first result value; using second adder to obtain the sum of first result value and second set value to produce second result value; using first comparator to compare first result value with a reference value so as to produce outupt clock; and using multitask device to select the information valve must be temporarity stored when the next system clock is triggered from first result value and second result value according to the quasi-position of output clock, so that the produced output clock frequency can be elastically set.

Description

technical field [0001] The present invention relates to a clock circuit, and in particular to a clock generating circuit and a generating method which can flexibly set the output clock frequency. Background technique [0002] In the electronic circuit system, in addition to the system clock provided by the system, other clocks with different frequencies from the system clock are often used. When the required clock frequency is an integer multiple of the system clock frequency, it can be achieved only by using a divider. However, in many cases, the required clock frequency and the frequency of the system clock cannot be exactly an integer multiple. For example, the 115.2KHz used by the serial port or the 44.1KHz used by the audio encoding and decoding often cannot be determined by the power of 2 ( 2 n ) divider to achieve. [0003] At this time, only the method of using a phase locked loop (Phase Lock Loop, PLL for short) or a digital state diagram (state machine) can be u...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H03L7/00
Inventor 李允国
Owner PROLIFIC TECH INC