Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Layout method of semiconductor integrated circuit, layout structure thereof, and photomask for forming the layout structure

一种集成电路、布局结构的技术，应用在半导体集成电路的光掩模领域，能够解决抗蚀构图维度偏移、焦点偏移、暴光光强度偏移等问题

Inactive Publication Date: 2005-02-23
KAWASAKI MICROELECTRONICS
View PDF2 Cites 20 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this extensive correction results in a reduction in the so-called processing margin
That is, it leads to the problem that resist patterns are susceptible to significant dimensional shifts due to exposure light intensity shifts, focus shifts, and so on over the exposed area

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Layout method of semiconductor integrated circuit, layout structure thereof, and photomask for forming the layout structure
  • Layout method of semiconductor integrated circuit, layout structure thereof, and photomask for forming the layout structure
  • Layout method of semiconductor integrated circuit, layout structure thereof, and photomask for forming the layout structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0167] Exemplary embodiments according to the present invention will now be described with reference to the accompanying drawings.

[0168] figure 1 An example of the layout structure of the semiconductor integrated circuit according to the present invention is shown.

[0169] figure 1 The illustrated layout structure includes a standard cell array 1 , a first adjacent dummy strip 2 along the vertical side of the standard cell array, and a second adjacent dummy strip 3 along the horizontal side of the standard cell array. A plurality of standard cells 10 distributed in the form of rows and columns forms a standard cell array 1 . The distributed multiple first adjacent dummy cells 20 form a first adjacent dummy strip 2 , and the distributed multiple second adjacent dummy cells 30 form a second adjacent dummy stripe 3 .

[0170] Each standard cell 10 has a circuit pattern (standard cell pattern), and has basic logic functions such as gates and flip-flops. The standard cell 1...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
wavelengthaaaaaaaaaa
Login to View More

Abstract

A plurality of standard cells 10 are arranged to form a channel-less standard cell array 1 , which has vertical and horizontal sides. A plurality of first proximity dummy cells 20 are arranged along each of the vertical sides of the standard cell array to form a first proximity dummy bands 20 such that the upper and lower sides of the first proximity dummy cells are in contact with each other and such that the left or right side of each of the first proximity dummy cells is in contact with the vertical side of the standard cell array 1 . Furthermore, a plurality of second proximity dummy bands are arranged along each of the horizontal sides of the standard cell array to form a second proximity dummy bands such that the upper or lower side of each of the second proximity dummy cells is in contact with the horizontal side of the standard cell 1.

Description

technical field [0001] The invention relates to a method for layout of a semiconductor integrated circuit on a computer, a layout structure of a semiconductor integrated circuit designed using the layout method, and a photomask for manufacturing a semiconductor integrated circuit with a layout structure. Background technique [0002] For designing the layout of semiconductor integrated circuits, standard cell methods are gaining popularity with the advancement of CAD (Computer Aided Design) tools. According to the standard cell method, various types of standard cells are designed, which have circuit diagrams, and are used to realize basic logic functions, such as gate circuits and flip-flops, etc., and the operation of standard cells has been verified in advance. The standard cells designed and verified in this way are registered in the library. The user selects standard cells from the library to achieve the desired logic function, and distributes these cells on the CAD too...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G03F1/36G03F1/70G06F17/50H01L21/027H01L21/82H01L21/822H01L27/02H01L27/04H01L27/118
CPCH01L27/11803H01L27/0207G06F17/5068G06F30/39
Inventor 前田润
Owner KAWASAKI MICROELECTRONICS
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com