The invention discloses an output buffering circuit which comprises a first-stage operational amplifying circuit, a second-stage operational amplifying circuit and a feedback circuit arranged between the first-stage operational amplifying circuit and the second-stage operational amplifying circuit. The first-stage operational amplifying circuit is used as a differential input circuit, the second-stage operational amplifying circuit is used as a common-source cascade amplifying circuit with an active load, and the feedback circuit is used for providing a bias voltage and having the driving capacity of alternatively providing a source current and a sink current. The first-stage operational amplifying circuit and the second-stage operational amplifying circuit form a unit gain amplifier through the feedback circuit, so that the whole circuit can have the driving capacity of alternatively providing the source current and the sink current. A special voltage stabilizing circuit is not required any more, the circuit structure is simple, the chip area can be reduced, power consumption can be further lowered due to the fact that the special voltage stabilizing circuit is not required any more, meanwhile, fluctuations of the output voltage can be restrained, the stability of the circuit during working is guaranteed, shifting is restrained to the maximum degree, an output signal is accurate, and a displayed image is good in quality.