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Detection for reducing soft error of hardware

A technology with errors and subtraction, which is applied to the redundancy in the calculation for data error detection, response error generation, etc., can solve the problems of large silicon cost and low cost performance

Inactive Publication Date: 2005-04-27
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In contrast, in most known systems, the detection of soft errors in combinational logic elements typically involves relatively expensive redundant hardware schemes
The downside of this approach is that providing sufficient hardware redundancy to detect soft errors in combinational logic is usually not cost-effective due to the considerable silicon cost of the redundant hardware

Method used

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  • Detection for reducing soft error of hardware
  • Detection for reducing soft error of hardware
  • Detection for reducing soft error of hardware

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Embodiment Construction

[0018] The following discussion sets forth numerous specific details in order to provide a thorough understanding of the invention. However, one of ordinary skill in the art having the benefit of this disclosure will recognize that the present invention may be practiced without these specific details. Also, various well-known methods, procedures, components and circuits have not been described in detail in order to focus attention on the characteristics of the present invention.

[0019] The hardware-reduced soft error detection embodiments discussed herein can be used with both signed and unsigned integer representations. Although much of the discussion below focuses on signed integers by way of example, those skilled in the art will recognize that signed integer representations may be used in conjunction with the soft error detection embodiments described herein, or unsigned integer representations may also be used. Integer representation.

[0020] As far as signed integer...

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Abstract

The soft error detection method and system for integral number addition and subtraction operation without adopting redundance logic is provided. For integral number addition and subtraction, the compensation logic generates the compensation value with the ALU result and operand. The compensation value is verified with the verification logic corresponding to the preset value to judge whether to have soft error. Under the hardware condition of carry transfer and no redundance, the compensation logic and the verification logic operate on the integral operand and the result ALU generates.

Description

technical field [0001] The present invention relates to systems for processing data, and more particularly to systems for detecting soft errors during execution in a computing environment. Background technique [0002] The phenomenon of soft errors is of increasing concern to processor designers. Soft errors are intermittent errors that occur during processor execution and are caused by alpha particles or high-energy neutrons in the atmosphere striking active regions of silicon, and are not due to design or manufacturing flaws . Soft errors alter the stored charge in memory cells and logic while leaving the physical circuit intact, producing incorrect behavior and results. Therefore, soft errors, also known as transient faults or single-event upsets (SEUs), result in an invalid state. [0003] Two sources of soft errors are high-energy neutrons and alpha particles. High-energy neutrons are the result of collisions between cosmic rays and atmospheric particles. Alpha par...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/14
Inventor S·马基内尼G·B·多施
Owner INTEL CORP
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