Programmable pipeline fabric utilizing partially global configuration buses
A global, bus technology, applied in general-purpose stored-program computers, architectures with multiple processing units, architectures with a single central processing unit, etc., can solve the problem that the hardware cannot use additional resources, and achieve the effect of effective use
Inactive Publication Date: 2005-10-26
CARNEGIE MELLON UNIV
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The static nature of this configuration leads to two important problems: the computation may require more hardware than is available, and the design of a single piece of hardware cannot take advantage of the additional resources that inevitably become available in future processing generations
For example, the input and output bus must be provided
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[0024] Figure 5 A hybrid association option in accordance with the teachings of the present invention is illustrated. exist Figure 5 It can be seen that virtual stripes 0, 1, 4, and 5 can be configured in physical stripes 10 and 12. More specifically, virtual stripes 0 and 4 may be configured in physical stripe 10 , and virtual stripes 1 and 5 may be configured in physical stripe 12 . Part of the global bus 13 may be used to transfer information required to configure physical stripes with virtual stripes.
[0025] Similarly, virtual stripes 2 and 6 can be used to configure physical stripe 14 , and virtual stripes 3 and 7 can be used to configure physical stripe 16 through the operation of part of global bus 17 . Such as Figure 5 As shown, the method of the present invention allows associating a first set of virtual stripes 0, 1, 4, 5 to at least two physical stripes 10, 12 while associating a second set of virtual stripes 2, 3, 6, 7 to at least two additional physical ...
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A method of associating virtual stripes to physical stripes in a pipelmed or ring structure comprises associating a first set of virtual stripes with at least two physical stripes and associating a second set of virtual stripes, disjoint from the first set, with at least two additional physical stripes. The present invention is also directed to a method of configuring a plurality of processing elements based on a less than global, but not purely local, association. The configuration method of the present invention may be implemented in a device arranged in stripes of processing elements. The method comprises configuring either of at least two physical stripes with a virtual stripe from a first set of virtual stripes and configuring either of at least two additional physical stripes with a virtual stripe from a second set of virtual stripes, said first and second virtual sets being disjoint. The present invention is also directed to a reconfigurable device comprising a controller, a memory device responsive to the controller, a plurality of processing elements arranged in stripes, a plurality of intrastripe interconnections for connecting processing elements within a stripe, a plurality of local inter-stripe connections for connecting the output of one stripe to the input of one and only one other stripe, a plurality of global inter-stripe connections for connecting at least one but less than all of the physical stripes to the memory, and an input bus and an output bus, each connected to at least one physical stripe.
Description
[0001] Statement Regarding Federally Funded Research [0002] This invention was developed in part with funding provided by DARPA-ITO / TTO under Contract No. DABT 63-96-C-0083. The federal government may have rights in this invention. technical field [0003] The present invention relates to reconfigurable architectures, and more particularly, to reconfigurable architectures for processing information in a pipelined fashion. Background technique [0004] Traditional approaches to reconfigurable computing statically configure programmable hardware to execute user-defined applications. The static nature of this configuration leads to two important problems: the computation may require more hardware than is available, and the design of a single piece of hardware cannot take advantage of the additional resources that inevitably become available in future processing generations. A technique called pipelined reconfiguration implements a large logical configuration on a small piec...
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IPC IPC(8): G06F9/38G06F15/78G06F15/80
CPCG06F15/7867G06F9/3897G06F9/38
Inventor H·施米特
Owner CARNEGIE MELLON UNIV