Column-decoding and precharging in a flash memory device

Abstract

The present invention describes methods of reading memory cells, and memory arrays using these methods. A group of memory cells is arranged in a rectangular array with rows (X-dimension) and columns (Y-dimension). In a row, the sources and drains of the memory cells are coupled to form a linear chain. A common word line is coupled to each gate in the row. Each node between adjacent memory cells in the chain is coupled to a separate column line. Four column Y-decoders are used to select column lines for sensing operations. In a sensing operation, a voltage source is provided to two of the four columns. During precharging, an electrical load is provided to the first node in the memory array. A second node separated from the first node on the same word line by at least one intervening node is precharged.

Description

field of invention [0001] The present invention generally relates to a memory cell array, and more particularly, the present invention relates to a virtual ground memory array. Background technique [0002] The architecture of general memory arrays is known in the art. Typically, a memory array contains multiple row and column lines. Rows in an array are often called word lines and columns are called bit lines, but the terms are relative. [0003] The overlapping part of the word line and the bit line is called a node (node). On or near each node is a memory cell, usually a transistor of some type. In a virtual ground architecture, one bit line can be used as a source or drain line for a transistor (memory cell) depending on whether the memory cell is program-verified or read. For simplicity of description, "read" may refer to a read operation or a program verify operation. [0004] Flash memory devices use memory cell transistors of a floating gate structure. Data in ...

AI Technical Summary

Problems solved by technology

So, estimating the proper amount of pre-charge voltage is difficult, and even more difficult for mirror-position architectures

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