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Input queue packet switch architecture and queue service discipline

An input queue, packet switching technology, applied in the field of packet switching node structure, can solve the problems of huge, packet throughput performance loss, high complexity, etc., to achieve the effect of reducing contention, significant performance gain, and increasing possibility

Inactive Publication Date: 2006-06-21
ALCATEL LUCENT SAS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] While other variations of the packet-switched fabrics described above have been the subject of intense research and development, a review of the literature shows that simple packet-switched fabrics such as input queuing structures and output queuing structures suffer from low packet throughput performance, while virtual output queuing structures such as Queue-structured complex packet-switched structures, resulting in huge development, maintenance and overhead costs due to the high complexity of their implementation

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  • Input queue packet switch architecture and queue service discipline
  • Input queue packet switch architecture and queue service discipline
  • Input queue packet switch architecture and queue service discipline

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Embodiment Construction

[0026] Going back to the typical first-in-first-out (FIFO) input queuing packet switching node architecture, each input port has a separate FIFO input queue, and specifically to why queue saturation is experienced on 58.58% packet throughput; it should be recognized that: Output port contention causes service to subsequently checked queues to be delayed until a subsequent queue service period regardless of the possibility of other packets destined for free output ports queued after the head-of-line packet!

[0027] So according to an exemplary embodiment of the present invention, the switching function of the packet switching node operates according to the exemplary embodiment of the present invention when selecting a packet for forwarding through a free output port, also taking into account the next-to-the-head in the input queue Packets following the grouping are not selected from the input queue for forwarding due to output port contention.

[0028]FIG. 2 shows the theoreti...

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Abstract

A packet switching node is described according to which a plurality of packets queued in an input queue are taken into account when selecting a packet for forwarding via a free output port. Accounting for multiple queued packets reduces the probability that an output port will remain idle and increases the probability that each input queue will be serviced despite blocking packet forwarding due to contention. Also described is the process of enqueuing and dequeuing packets from input queues, each input queue having associated therewith a plurality of head-of-line registers pointing to a corresponding sequence of head-of-line queue entries. Enqueueing ensures that the correct head-of-line registers point to the sequence of head-of-line queue entries in turn. Service each input queue dequeue entry in order, and dequeue ensures reordering of head of queue pointers. Advantages are gained from reducing the likelihood of output ports remaining idle while increasing the likelihood of servicing input queues, thus reducing the adverse effects of contention and increasing packet throughput.

Description

technical field [0001] The present invention relates to the packet switching node structure, and specifically relates to the input queuing packet switching node structure and queue service rules. Background technique [0002] Much of the packet-switching infrastructure in use today operates on the basis of store-and-forward packet processing rules. The commonly used Internet Protocol (IP) is an example of a packet transport protocol following the store-and-forward rule. Each IP packet has a header portion and a payload portion of variable length. Deterministic resources include: packet transmission bandwidth on communication links interconnecting packet switching nodes, packet storage on packet switching nodes, and packet processing bandwidth on packet switching nodes. [0003] Assuming that sufficient storage is available at the packet switching nodes, packets are transmitted over the interconnecting links, which are subject to the transmission bandwidth available on the ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/56
CPCH04L49/103H04L49/254H04L49/3018H04L49/351H04L49/508
Inventor P·拉比诺维奇W·奥列辛斯基
Owner ALCATEL LUCENT SAS