Memory controller to utilize dram write buffers

Abstract

A method, an apparatus, and a computer program are provided to account for data stored in Dynamic Random Access Memory (DRAM) write buffers. There is difficulty in tracking the data stored in DRAM write buffers. To alleviate the difficulty, a cache line list is employed. The cache line list is maintained in a memory controller, which is updated with data movement. This list allows for ease of maintenance of data without loss of consistency.

Description

technical field [0001] The present invention relates generally to dynamic random access memory (DRAM) write buffers, and more particularly to memory controllers utilizing DRAM write buffers. Background technique [0002] In the current DRAM design, DRAM often uses a single port to drive write data and sense (sense) read data. A bidirectional bus is used, and since these two different operations utilize this resource, conflicts often arise in the receiving device. Therefore, the delay will cause a write-to-read turnaround due to this conflict. Each delay would then collectively degrade the performance of the usual memory. [0003] To prevent (combat) delays associated with resource conflicts caused by write-to-read inversion, Extreme Data Rate (XDR TM ) DRAM can employ a write buffer (WB). WB allows XDR TM DRAM (XDRAM) and some other DRAMs keep one or more cache lines in a buffer that are not actually written to the XDRAM core. A cache line can be 128 bytes, but can be ...

AI Technical Summary

Problems solved by technology

[0004] However, maintaining WB accounting by the memory controller is difficult and requires additional hardware

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