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Semiconductor integrated circuit device and method of manufacturing the same

A technology of integrated circuits and semiconductors, which is applied in the field of analog semiconductor devices and can solve the problems of increasing chip area and so on.

Inactive Publication Date: 2006-08-16
SII SEMICONDUCTOR CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0009] like Figure 13B , 14B and 15B, in the case of forming an ESD protection device in a semiconductor thin film layer on an SOI substrate, the size of the protection device must be large or many protection devices are required in order to obtain sufficient ESD resistance, resulting in a chip area due to protection increase in circuit area

Method used

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  • Semiconductor integrated circuit device and method of manufacturing the same
  • Semiconductor integrated circuit device and method of manufacturing the same
  • Semiconductor integrated circuit device and method of manufacturing the same

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Embodiment Construction

[0078] Embodiments of the present invention will be specifically described below with reference to the drawings. figure 1 is a schematic cross-sectional view of an embodiment of a semiconductor integrated circuit device according to the present invention. Figure 2A and 2B , image 3 , Figure 4A and 4B shown in the figure 1 A protection circuit for internal elements formed in a semiconductor integrated circuit device.

[0079] figure 1 The SOI substrate in is composed of the following parts: For example, a semiconductor support substrate 101 made of P-type single crystal silicon; a buried insulating film 103; a semiconductor thin film layer made of P-type single crystal silicon for constituting a device 102. Formed on the P-type semiconductor thin film layer 102 are a CMOS inverter 11 and a P-type conductivity resistor (P-resistor) 115 . The CMOS inverter 11 is used as an internal element 10 composed of a first N-channel MOS transistor (hereinafter referred to as N...

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Abstract

An ESD protection circuit with a reduced area is provided whose ESD protection device protects an internal element against ESD while ensuring sufficient. ESD strength in a power management semiconductor device having a fully depleted SOI device structure and in an analog semiconductor device. An NMOS protection transistor formed on an SOI semiconductor thin film layer is used as the ESD protection device at an output terminal of an internal element that is a fully depleted SOI CMOS formed on a semiconductor thin film layer, especially an NMOS output terminal, while an NMOS protection transistor formed on a semiconductor support substrate is used for input protection of the internal element.

Description

technical field [0001] The present invention relates to power management semiconductor devices and analog semiconductor devices with low voltage operating field effect transistors having a fully depleted SOI device structure. Background technique [0002] Semiconductor integrated circuit devices use field effect transistors (such as N-type and P-type MOS transistors) and resistors made of polysilicon to provide input protection devices or output protection devices between internal circuits and external input / output terminals to avoid It is common practice to damage internal elements constituting an internal circuit due to overcurrent input, for example, caused by static electricity. An example of an input / output circuit block in a semiconductor integrated circuit device having such a conventional protection circuit can be seen in Figure 13A and 13B , Figure 14A and 14B as well as Figure 15A and 15B . [0003] Figure 13A and 13B A CMOS inverter 11 is shown, which i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/092H01L21/8238
CPCH01L27/0266H01L27/04
Inventor 长谷川尚吉田宜史
Owner SII SEMICONDUCTOR CORP