Dual thread processor

Abstract

A pipeline processor architecture, processor, and methods are provided. In one implementation, a processor is provided that includes an instruction fetch unit operable to fetch instructions associated with a plurality of processor threads, a decoder responsive to the instruction fetch unit, issue logic responsive to the decoder, and a register file including a plurality of banks corresponding to the plurality of processor threads. Each bank is operable to store data associated with a corresponding processor thread. The processor can include a set of registers corresponding to each of a plurality of processor threads. Each register within a set is located either before or after a pipeline stage of the processor.

Description

technical field [0001] The following disclosure relates to processing circuits and systems. Background technique [0002] Conventional operating systems typically support multitasking, which is a scheduling mechanism that allows more than one processor thread to share common processing resources. Processor threads represent architectural state within the processor that tracks the execution of software programs. If a computer has a single processor, only one processor thread is being processed at any given point in time, which means that the processor is now effectively executing the instructions associated with that single processor thread. The act of reallocating a processor from one processor thread to another is called a context switch or context switch. [0003] In conventional pipelined processors, context switching usually occurs through hardware interrupts and interrupt service routines. Interrupt service routines often have associated execution time or interrupt o...

AI Technical Summary

Problems solved by technology

Interrupt service routines often have associated execution time or interrupt overhead, consuming valuable processor time

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