Demonstration system for phase-change memory cell array and visual demonstration method therefor
A phase-change memory and cell array technology, applied in the field of micro-nano electronics, can solve problems such as the inability to realize intuitive visualization operations
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Embodiment 1
[0026] Figure 6 It is a schematic diagram of the readout circuit, switching circuit, and address selection circuit in the first column of a demonstration system with a phase-change memory device cell array of 8×8, and the other seven columns have the same principle. Among them, Q9 is an analog device ADG706BRU. Its function is that when the EN terminal is at a high level, the D port will select one of the S[16-1] according to the input signal of the port A[3-0]. Its function is equivalent to 4 -16 multiplexer. It is used as an address selection circuit here, where EN is connected to the column selection signal such as SAMPLECIL0, A[2-0] is connected to the row selection signal of this column such as SAMPLEROW[2-0], and S[8-1] is connected to the eighth of a certain column. A storage unit such as SAMPLE[70-00], D is connected to the output terminal of the sample such as SAMPLEOUT0, and the other seven columns are also connected in the same relationship.
[0027] Among them, ...
Embodiment 2
[0030] Figure 7 is the pair in the Phase Change Memory Device Cell Array Demonstration System Figure 6 The switching circuit, the address selection circuit, the control circuit controlled by the readout circuit and the interface circuit connected with the programmable logic device are shown. Among them, J1 is the interface circuit connected with the programmable device and U1, U2, and U2 is a flip-flop of model 74HC574, and its function is to input D when the clock input CLK is a rising edge when the enable terminal OC is not active at low level. [8-1] are all sent to the output terminal of Q[8-1], where the enable terminal is grounded, the clock input is connected to the column selection enable signal CS_COL of J1, and Q[8-1] is connected to Figure 6 The column selection signal SAMPLECOL[0-7], D[8-1] are connected to the data signal MCU-AD[0-7] of J1 connected by the programmable device. U1 is a buffer with a model of 74HC245. Its function is to output the data signal fr...
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