Method and arrangment for testing a stacked die semiconductor device

Abstract

A semiconductor device and related testing methods and configurations are provided to enable parallel (simultaneous) testing of multiple chips on a stacked multiple chip semiconductor device. Each chip in the device is configured to selectively output test results to one or more unique contacts on a substrate of the device.

Description

technical field [0001] The present invention relates to semiconductor devices, and more particularly to an arrangement for simultaneously testing multiple chips or dies of a stacked die semiconductor device. Background technique [0002] Semiconductor devices can be packaged in a variety of ways depending on the application of the device. One packaging technique involves stacking multiple semiconductor integrated circuit "chips" or dies, and routing connection traces to each chip from a common substrate. Stacked die packaging is common in semiconductor memory device applications such as dynamic random access memory (DRAM) devices. [0003] This device presents challenges when testing stacked die devices. In the current design, an example of which is shown in Figure 1, similar functional pins on each die are connected to similar functional contacts on the substrate. There is a top die or chip 10 , a bottom chip 20 and a substrate 30 . So-called "DQ" or pins such as DQ0 on...

AI Technical Summary

Problems solved by technology

Therefore, the test result data signals from the test programs performed on the die will interfere with each other if read out simultaneously through the contacts on the substrate

Images