Device and method for transmitting data in asynchronous clock domain

Abstract

A method for transmitting data in asynchronous clock domain includes storing data into storage unit and generating a data ready indication signal being sent to receiving party by sending party when energized writing signal is valid, generating data indication signal by receiving party when edge of said indication signal is detected, regulating phase of the first counter according to said indication signal and fetching data from storage unit when phase of the first counter is on preset phase.

Description

technical field [0001] The invention relates to the technical field of data transmission, in particular to a device and method for transmitting data in an asynchronous clock domain. Background technique [0002] In most systems, data is transmitted between different boards in a serial manner, while asynchronous clocks are used between different boards. However, even if the asynchronous clocks of different boards have the same source, because they are obtained through different phase-locked loops (PLL) or different channels, the respective clock signal jitters (Jitter) are different, and in any There will be a frequency difference in a short period of time, but the long-term statistical results show that they are synchronized to the clock source, so two clocks on different boards will have phase drift within a certain period of time, and the maximum value of the phase drift depends on The quality of components such as clock sources and PLLs. [0003] Most systems today use ...

AI Technical Summary

Problems solved by technology

However, when any of the read and write ports of the FIFO is abnormal and the read and write addresses jump, the FIFO cannot detect it, and it is impossible to adjust the transmission delay of the data in the FIFO, so the FIFO cannot meet the requirements for the transmission delay. Error Sensitive Applications

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