Bus address selecting circuit and bus address selecting method

Abstract

A bus address selecting circuit is disclosed that selects addresses to be output to a first address bus connected to a first memory and a second address bus connected to a second memory, the bus address selecting circuit comprising an address output circuit that, based on a selecting bit composed of a predetermined plurality of bits in an instruction code, outputs addresses stored in first and second address registers out of a plurality of address registers as first and second addresses; and a bus selecting circuit that, based on predetermined higher-order n bits of at least one of the first and second addresses, outputs the first address to one of the first and second address buses and the second address to the other of the first and second address buses.

Description

technical field [0001] The invention relates to a bus address selection circuit and a bus address selection method. Background technique [0002] A processing circuit such as a DSP (Digital Signal Processor) may incorporate a plurality of memories in order to perform data processing at high speed (see, for example, Non-Patent Document 1). FIG. 7 is a diagram showing a general configuration example of a DSP having two memories (SRAM: Static Random Access Memory). The DSP 100 is configured to include: a DSP core (core) 110 that executes data processing; and SRAMs 121 and 122 that store various data. Furthermore, SRAM 121 is connected to address bus A131, and SRAM 122 is connected to address bus B141. [0003] The DSP core 110 is configured to include a command register 151 , a decoder 152 , a control circuit 153 , a plurality of address registers 154 , and a selector 155 . The command register 151 stores a command code read from a ROM (Read Only Memory) not shown in the fig...

AI Technical Summary

Problems solved by technology

Therefore, it is also considered that the address register E can be used even in processing (2) by increasing the combination of address registers illustrated in FIG. 200 digits will increase

[0011] In addition, as described above, since the addresses to be output to the address bus 131 and the address bus 141 are selected according to the order of program description, the degree of freedom at the time of program description is low.

In addition, in the program, which one of the address buses 131 and 141 to be output to the specified address bus 131, 141 should also be considered, and the code used to represent the specification is required, so the number of bits of the command code 200 will increase.

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