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Method and apparatus for simple pulse interpolation

A pulse, simple technology, applied in the direction of automatic power control, electrical components, etc., can solve problems such as output jitter, loop instability, complex circuit structure, etc., achieve fast response speed, simple circuit structure, and wide application prospects

Inactive Publication Date: 2011-03-30
SHANGHAI BEILING
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] However, although it has excellent phase-locked-frequency-locked functions, the design involving phase-locked loop technology often faces problems such as complex circuit structure, loop instability, and output jitter.

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  • Method and apparatus for simple pulse interpolation
  • Method and apparatus for simple pulse interpolation
  • Method and apparatus for simple pulse interpolation

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Embodiment Construction

[0025] Such as Figure 4 As shown, the simple pulse interpolation device of the present invention includes a reversible counter 1, a frequency divider 2 and an oscillator 3 connected in sequence, wherein:

[0026] Oscillator 3, is used for providing the input pulse of described up-down counter;

[0027] The frequency divider 2 is used to perform frequency division processing on the output pulse of the oscillator according to the control signal;

[0028] Reversible counter 1 is used to output a narrow pulse signal when the counter counts to the set value.

[0029] The pulse S1 shown in Figure 3(a) is used as the control terminal signal of the reversible counter (up / down counter). The counting input pulse CP is provided by an internal oscillator with a natural frequency of f osc . When using the addition counter function, the output pulse of the oscillator is processed by frequency division, and the frequency is reduced to When using the down counter function, the oscillat...

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Abstract

A simple pulse interpolation method and device, the method including the following processes: according to the pulse control signal arriving to the control end, on the one hand, the divider processes frequency-dividing on the natural frequency of the oscillator, on the other hand, a reversible counter chooses a counting method, and then, according to the determined counting mode and frequency-dividing result to process counting; after one cycle, T time, of the control end signal, and when next pulse control signal of the control end coming, the reversible counter chooses another counting mode, and meanwhile, the frequency divider re-divides the natural frequency of the oscillator, and then according to the determined counting mode and frequency-division result to process counting, until the configured value, and at this time outputting a narrow pulse signal. Therefore, the frequency and phase of the output pulse, and the phase of the control end maintain the configured relationship. The invention provides a simple pulse interpolation algorithm that can achieve locking phase and locking frequency effects, and without feedback and comparison process, and circuit structure is simple,response speed fast, and it has a broad application prospects.

Description

technical field [0001] The invention relates to a simple pulse interpolation method and device. Background technique [0002] At present, the conventional pulse interpolation method is often completed by using a Phase Locked Loop (Phase Locked Loop, PLL) technology. Using phase-locked loop technology, it is possible to obtain output pulses that are proportional to the input pulse frequency and have a constant phase difference. This feature is widely used in many fields such as communications, electronics, and measurement and control. [0003] Phase-locked loop technology, also known as automatic phase control technology, was developed in the 1930s. Its structure is as follows: figure 1 As shown, it is mainly composed of a phase detector (PD), a loop filter (LF), and a voltage-controlled oscillator (VCO). [0004] The basic principle is as follows: PD will input the signal S 1 (frequency f 1 , with a phase of φ 1 ) and the output signal S that has been multiplied / divided...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/18
Inventor 王小明陈聪
Owner SHANGHAI BEILING