Dynamically-tunable memory controller

a memory controller and dynamic technology, applied in the field of dynamically-tunable memory controllers, can solve the problem that the array may take up a rather large area

Inactive Publication Date: 2002-01-31
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

While a two-dimensional array may be used to represent sets of parameter values, an array may take up a rather large area on an integrated circuit device, particularly due to redundant data in the array.

Method used

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Embodiment Construction

signal that is selectively asserted by controller / sequencer 222 when in a test mode. Consequently, when in a test mode, the value of the TEST VALUE signal is provided as the CURRENT VALUE signal, and when in a non-test, or operational mode, the FINAL VALUE signal is provided as the CURRENT VALUE.

[0138] The TEST VALUE inputs to registers 260, 262 are respectively gated by UPDATE PASS and UPDATE FAIL signals selectively asserted by controller / sequencer 222. The UPDATE PASS signal is asserted whenever the last test initiated by controller / sequencer 222 resulted in a "pass" result from memory test controller 228. Similarly, the UPDATE FAIL signal is asserted whenever the last test initiated by controller / sequencer 222 resulted in a "fail" result from memory test controller 228. Assertion of one of the UPDATE PASS and UPDATE FAIL signals corresponds generally to block 258 of FIG. 14.

[0139] Consequently, whenever a test results in a "pass" result, register 260 is updated with the average ...

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PUM

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Abstract

A memory controller circuit arrangement and method utilize a tuning circuit that dynamically controls the timing of memory control operations, rather than simply relying on fixed timing parameters that are either hardwired or initialized upon startup of a memory controller. Dynamic control over the timing of memory control operations typically incorporates memory test control logic that verifies whether or not a memory storage device will reliably operate using the dynamically-selected values of given timing parameters. Then, based upon the results of such testing, such dynamically-selected values are selectively updated and retested until optimum values are found. The dynamically-selected values may be used to set one or more programmable registers, each of which may in turn be used to control the operation of a programmable delay counter that enables a state transition in a state machine logic circuit to initiate performance of a memory control operation by the logic circuit. Dynamic tuning may also utilize a unique binary search engine circuit arrangement that updates one of two registers with an average of the current values stored in such registers based upon the result of a test performed using that average value. By selectively updating such registers, a fast convergence to an optimum value occurs with minimal circuitry.

Description

[0001] This application is a continuation-in-part of U.S. patent application Ser. No. 09 / 166,004, filed Oct. 2, 1998 by Gary Paul McClannahan, and entitled "MEMORY CONTROLLER WITH PROGRAMMABLE DELAY COUNTER FOR TUNING PERFORMANCE BASED ON TIMING PARAMETER OF CONTROLLED MEMORY STORAGE DEVICE," which application is incorporated by reference herein.[0002] The invention is generally related to integrated circuit device architecture and design, and in particular to the architecture and design of a memory controller for controlling data transfer with a memory storage device.[0003] Computers and other data processing systems rely extensively on various memories to store information used by such systems in performing computer tasks. A memory may be used, for example, to store a portion of a computer program that is executed by a computer, as well as the data that is operated upon by the computer.[0004] Memories may also be found in many of the components of a computer. For example, a microp...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F12/00G06F13/16
CPCG06F13/1694G06F12/00
Inventor DELP, GARY SCOTTMCCLANNAHAN, GARY PAUL
Owner INT BUSINESS MASCH CORP
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