Dynamically-tunable memory controller
a memory controller and dynamic technology, applied in the field of dynamically-tunable memory controllers, can solve the problem that the array may take up a rather large area
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signal that is selectively asserted by controller / sequencer 222 when in a test mode. Consequently, when in a test mode, the value of the TEST VALUE signal is provided as the CURRENT VALUE signal, and when in a non-test, or operational mode, the FINAL VALUE signal is provided as the CURRENT VALUE.
[0138] The TEST VALUE inputs to registers 260, 262 are respectively gated by UPDATE PASS and UPDATE FAIL signals selectively asserted by controller / sequencer 222. The UPDATE PASS signal is asserted whenever the last test initiated by controller / sequencer 222 resulted in a "pass" result from memory test controller 228. Similarly, the UPDATE FAIL signal is asserted whenever the last test initiated by controller / sequencer 222 resulted in a "fail" result from memory test controller 228. Assertion of one of the UPDATE PASS and UPDATE FAIL signals corresponds generally to block 258 of FIG. 14.
[0139] Consequently, whenever a test results in a "pass" result, register 260 is updated with the average ...
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