Structure for preventing salicide bridging and method thereof

Abstract

A semiconductor device having a memory array that includes a plurality of substantially parallel word lines, a plurality of substantially parallel bit lines, wherein each of the plurality of the word lines is substantially perpendicular to each of the plurality of the bit lines, a first dummy word line disposed at a periphery of the memory array, wherein the first dummy word line is substantially parallel to the plurality of word lines and overlaps at least two non-adjacent bit lines.

Description

DESCRIPTION OF THE INVENTION[0001] 1. Field of the Invention[0002] This invention pertains in general to a semiconductor device and, more particularly, to a structure for preventing salicide bridging in a semiconductor device and a method thereof.[0003] 2. Background of the Invention[0004] In modern memory integrated circuits ("ICs"), an important consideration is the speed that stored data may be read or retrieved. Such speed depends partly on the speed of word lines. In the semiconductor industry's continued effort to reduce feature sizes of ICs, the width of word lines is also reduced. Such a reduction leads to an increase in the resistance of the word lines. As is known, higher resistance on a word line reduces its speed, which, in turn, reduces the speed of the memory IC. In order to fabricate high performance ICs, low resistivity on the word line is therefore critical.[0005] In conventional metal-oxide semiconductor ("MOS") ICs, polysilicon is often used as the gate material. ...

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Benefits of technology

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Problems solved by technology

Such a reduction leads to an increase in the resistance of the word lines.

As is known, higher resistance on a word line reduces its speed, which, in turn, reduces the speed of the memory IC.

However, a possible result is that salicides may be unintentionally formed over some active regions that cannot be masked, such as the source and / or drain regions, during a particular step of the manufacturing process.

Slicide bridging is undesirable because it may render an IC inoperative.

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