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Universal test interface between a device under test and a test head

a test head and universal technology, applied in the direction of measurement devices, electronic circuit testing, instruments, etc., can solve the problems of complicated solution, increased difficulty in work, and troublesome use of solder connections

Inactive Publication Date: 2005-02-24
ADVANTEST CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0014] It is an object of the invention to provide a connection system between devices under test and a test head that provides a secure modular connection to the devices under test for high data rates without causing degradation in signal quality.
[0015] It is a further object of the invention to provide a high density, scalable connection system between devices under test and a test head.
[0020] According to another embodiment of the present invention, an interface to perform high-parallelism testing of memory devices comprises a first board holding one of the memory devices and having a receptacle connected to the one memory device, and a plug connected to respective cables and to the receptacle to create a communication pathway, wherein combinations of the first boards and the plugs allow high-parallelism testing of the memory devices.
[0023] According to still another embodiment of the present invention, a method of connecting a memory device on a DUT board to cables for high-parallelism testing of memory devices that comprises unplugging a first DUT board having a first receptacle from a plug connected to respective cables, and plugging a second DUT board having a second receptacle into the plug to form a communication pathway between the memory device and the cables, wherein combinations of the second DUT boards and the plugs allow high-parallelism testing of the memory devices.

Problems solved by technology

This use of solder connections is problematic since it is time consuming to attach the cables 70 to the solder points 82 of the DUT boards 80.
However, this solution also is problematic as the number and density of DUTs 60 being tested increases.
As the pogos 100 get smaller, they become more delicate and difficult to work with.
This increases the production cost for the pogo boards 110 and the DUT boards 80.
In addition, pogos 100 are themselves expensive to use.
Such a configuration is unsuitable for high-density, high-parallelism testing of DUTs, especially where the DUT is a smaller device such as a memory device.
Thus, for high-parallelism testing of memory devices (i.e., simultaneous testing of 32 or more devices), conventional plug arrangements were not possible.

Method used

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  • Universal test interface between a device under test and a test head
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  • Universal test interface between a device under test and a test head

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Embodiment Construction

[0038] Reference will now be made in detail to the present preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures.

[0039] For an embodiment of the present invention shown in FIGS. 5A through 6B, an array of shielded controlled impedance (SCI) connectors 220 are disposed in connector openings 249 in a board spacer 230. Each SCI connector 220 is connected to a cable 70, which extends through cable openings 247 in the board spacer 230. The relative size of the cable openings 247 and connector openings 249 forming array holes 245 restrains the movement of the SCI connector 220 in the X, Y and Z directions, and prevents the SCI connectors 220 from being pulled through into the interface. The array holes 245 are arranged as part of a larger array 240 on the b...

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Abstract

In order to form a modular interface between a DUT board, which is housing devices under tests (DUT), to cables connected to a test head, a board spacer is provided that has an array of connectors. Each cable is connected to a respective connector, and the DUT board contains a corresponding array of connection points which are less than or equal to the number of connectors in the arrays on the board spacer. In this way, a common board spacer can be used to connect the cables to DUT boards housing different types of DUTs since the location of the connection points on the board spacer is known and kept constant. This interface allows a high speed and high fidelity connection between the test head and the devices on the DUTs for frequencies in excess of 50 MHz.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of U.S. patent application Ser. No. 10 / 326,392, filed Dec. 23, 2002 in the United States Patent and Trademark Office, which is a divisional of U.S. patent application Ser. No. 09 / 808,009, filed Mar. 15, 2001 in the United States Patent and Trademark Office, the disclosures of which is incorporated herein by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention relates generally to automatic test equipment used to test integrated circuit elements, and more particularly to interface hardware used in automatic test equipment to connect devices under test to a test head in order to perform the testing. [0004] 2. Description of the Related Art [0005] Automatic test equipment (i.e., a tester) is generally used to test semiconductor devices and integrated circuit elements, such as memory or logic for manufacturing defects. A general representation of a tester is shown in F...

Claims

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Application Information

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IPC IPC(8): G01R1/073G01R31/28
CPCG01R31/2886G01R1/07378G01R21/00
Inventor FRAME, JAMES WARREN
Owner ADVANTEST CORP