Method for using ion implantation to treat the sidewalls of a feature in a low-k dielectric film

Abstract

A method for forming a mechanically strengthened feature in a low-k dielectric film on a substrate includes using either spin-on-dielectric (SOD) techniques, or chemical vapor deposition (CVD) techniques to form a low-k dielectric film on the substrate. A sidewall of the feature in the low-k dielectric film is then treated in order to increase the film's mechanical strength. Treatment of the sidewall of the feature in the low-k dielectric film comprises forming a hardened layer by subjecting the low-k dielectric film to low energy, high flux ion implantation. Process parameters of the ion implantation are selected such that the implantation process does not cause a substantial change in the dielectric constant of the low-k dielectric film.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is related to and claims priority to U.S. provisional application Ser. No. 60 / 489,100 filed on Jul. 23, 2003; the entire contents of which are herein incorporated by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a method for treating a low-k dielectric film, and, more particularly, to a method for using ion implantation to treat the sidewalls of a feature in a low-k dielectric film following an etch process. [0004] 2. Description of Related Art [0005] As is known to those in the semiconductor art, interconnect delay is a major limiting factor in the drive to improve the speed and performance of integrated circuits (IC). One way to minimize interconnect delay is to reduce interconnect capacitance by using low dielectric constant (low-k) materials during production of the IC. Thus, in recent years, low-k materials have been developed to replace relatively hi...

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Benefits of technology

[0007] One aspect of the present invention is to reduce or eliminate any or all of the above-described problems.

Problems solved by technology

As is known to those in the semiconductor art, interconnect delay is a major limiting factor in the drive to improve the speed and performance of integrated circuits (IC).

However, one drawback to using low-k films in semiconductor manufacturing is that such films have demonstrated a low mechanical strength.

This makes the films susceptible to damage in downstream process steps, such as during chemical-mechanical polishing (CMP), resulting in low product yields and / or decreased device reliability.

This low mechanical strength of low-k films has prevented them from receiving widespread acceptance by device manufacturers.

Thus, the performance advantages to using low-k films have been largely unrealized.

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